From patchwork Mon Apr 23 09:14:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 8027 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id AEF5523E23 for ; Mon, 23 Apr 2012 09:14:49 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 7697BA1822A for ; Mon, 23 Apr 2012 09:14:49 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so22452743iag.11 for ; Mon, 23 Apr 2012 02:14:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:mime-version:content-type :x-gm-message-state; bh=rvtZmixuqS9y7Wq4SGodZEoPmOyKKvy+r+HdkDQovdc=; b=amARZUK9JINJ13VRZL9Pmy5URf5pQ6JiXKGTswOpFmqMliD3h21DAx/3o+SVVDTSIg WnHfeSKDEoYCUfNuBj9+z1QukhlOXG8IPO5JBwTuRdEUDfzaTm97y+0ewy8y1YghIMco RQS3LVrRC4OPaE7JJyiNrhD9Ixwqv7xzuFqerlflcSGi+MfS2LOXZDP1UmM792XMjoYb EXfDRLuv2QNYiKmE4yX7e1CX6IY3yYmMowisNzns8RysESptMGVgr5csmUmmIYWieuwT 3RDHAx/oPNrRlDa3SXl3wRoiswOLzG/TEWZxVG67OILkT8L8SG5OppHnH32qlaawTxHw 00+Q== Received: by 10.50.193.199 with SMTP id hq7mr5527606igc.49.1335172489211; Mon, 23 Apr 2012 02:14:49 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp97937ibt; Mon, 23 Apr 2012 02:14:48 -0700 (PDT) Received: by 10.14.98.143 with SMTP id v15mr2408638eef.90.1335172487894; Mon, 23 Apr 2012 02:14:47 -0700 (PDT) Received: from eu1sys200aog110.obsmtp.com (eu1sys200aog110.obsmtp.com. [207.126.144.129]) by mx.google.com with SMTP id a45si4191239eeg.162.2012.04.23.02.14.41 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 23 Apr 2012 02:14:47 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.129 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.129; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.129 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob110.postini.com ([207.126.147.11]) with SMTP ID DSNKT5UdgTj2ihrVVZxrhl2LA+Vb9d3PRyCM@postini.com; Mon, 23 Apr 2012 09:14:47 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 05C431BA; Mon, 23 Apr 2012 09:14:38 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 66B5C24FB; Mon, 23 Apr 2012 09:14:38 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id E9B0E24C2F1; Mon, 23 Apr 2012 11:14:32 +0200 (CEST) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Mon, 23 Apr 2012 11:14:37 +0200 From: Linus Walleij To: , Cc: Grant Likely , Philippe LANGLAIS , Rabin Vincent , Jonas Aberg , Lee Jones , Linus Walleij Subject: [PATCH 4/9] gpio/nomadik: support low EMI mode Date: Mon, 23 Apr 2012 11:14:35 +0200 Message-ID: <1335172475-27613-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.9.2 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQm0o4xTlDWAMv6gZHrZ8KNHYkpkot9FwVZU/ncSho0MxfVk+frUAYCMwbOU4HMnvvskJjX1 From: Rabin Vincent Low EMI (Electro-Magnetic Interference) mode means lower slew rate on the signals. The Nomadik GPIO controller supports this so create an interface to enable it. Signed-off-by: Rabin Vincent Reviewed-by: Srinidhi Kasagar Signed-off-by: Linus Walleij --- arch/arm/plat-nomadik/include/plat/gpio-nomadik.h | 1 + arch/arm/plat-nomadik/include/plat/pincfg.h | 6 +++++ drivers/gpio/gpio-nomadik.c | 25 +++++++++++++++++++++ 3 files changed, 32 insertions(+) diff --git a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h index 9605bf2..3e8b7f1 100644 --- a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h +++ b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h @@ -29,6 +29,7 @@ #define NMK_GPIO_SLPC 0x1c #define NMK_GPIO_AFSLA 0x20 #define NMK_GPIO_AFSLB 0x24 +#define NMK_GPIO_LOWEMI 0x28 #define NMK_GPIO_RIMSC 0x40 #define NMK_GPIO_FIMSC 0x44 diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h index 22cb97d..da6b1e3 100644 --- a/arch/arm/plat-nomadik/include/plat/pincfg.h +++ b/arch/arm/plat-nomadik/include/plat/pincfg.h @@ -105,6 +105,12 @@ typedef unsigned long pin_cfg_t; #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) +#define PIN_LOWEMI_SHIFT 25 +#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) +#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) +#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) +#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) + /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) diff --git a/drivers/gpio/gpio-nomadik.c b/drivers/gpio/gpio-nomadik.c index 681daee..7b45d88 100644 --- a/drivers/gpio/gpio-nomadik.c +++ b/drivers/gpio/gpio-nomadik.c @@ -61,6 +61,7 @@ struct nmk_gpio_chip { u32 rimsc; u32 fimsc; u32 pull_up; + u32 lowemi; }; static struct nmk_gpio_chip * @@ -125,6 +126,24 @@ static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, } } +static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, + unsigned offset, bool lowemi) +{ + u32 bit = BIT(offset); + bool enabled = nmk_chip->lowemi & bit; + + if (lowemi == enabled) + return; + + if (lowemi) + nmk_chip->lowemi |= bit; + else + nmk_chip->lowemi &= ~bit; + + writel_relaxed(nmk_chip->lowemi, + nmk_chip->addr + NMK_GPIO_LOWEMI); +} + static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, unsigned offset) { @@ -269,6 +288,8 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, __nmk_gpio_set_pull(nmk_chip, offset, pull); } + __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg)); + /* * If the pin is switching to altfunc, and there was an interrupt * installed on it which has been lazy disabled, actually mask the @@ -1181,6 +1202,10 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) chip->dev = &dev->dev; chip->owner = THIS_MODULE; + clk_enable(nmk_chip->clk); + nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); + clk_disable(nmk_chip->clk); + ret = gpiochip_add(&nmk_chip->chip); if (ret) goto out_free;