From patchwork Mon Oct 15 21:51:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Vorontsov X-Patchwork-Id: 12239 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3B27E23EFB for ; Mon, 15 Oct 2012 21:54:39 +0000 (UTC) Received: from mail-ia0-f180.google.com (mail-ia0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id C6936A1861A for ; Mon, 15 Oct 2012 21:54:38 +0000 (UTC) Received: by mail-ia0-f180.google.com with SMTP id f6so3982751iag.11 for ; Mon, 15 Oct 2012 14:54:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=oXk1S5MqB6NtrtSJ1tapRDTZDgQ3x6fZWvNcYKm/6N0=; b=SdeJTFXT6idWsBIzedwJikRkJjzqzURoV8XNftqUteXl6tdWgJ6ObLWwQxyX+/Qi84 ribBsJqoZWk+YGBoE2XoLxb/kNVKIl0Hd5fXtCMDhnr/kRs+s/oQDEPm8u/HK+EhK8bh O2CKvjiPsR/+GcEzNsT91WzovIjAFa3/9sA99EZ6CWvazmN7wYX6ohKfSq3KkWoDypyp zzSu8jicGhDPgEovbalq4sxFtz1hWiF3z6cizsY6uRJfgtjyb4eGaz8Qj4M6yA4BZkT1 g7krAZuQ7ptv26irXdmv2Yuwr6BzB9dzIOqVfTViTrZpZc1bYO8SLZ06ek6V+D4XPX89 u8MA== Received: by 10.50.87.134 with SMTP id ay6mr10047798igb.70.1350338078250; Mon, 15 Oct 2012 14:54:38 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp641620igt; Mon, 15 Oct 2012 14:54:37 -0700 (PDT) Received: by 10.68.238.34 with SMTP id vh2mr41473814pbc.6.1350338077462; Mon, 15 Oct 2012 14:54:37 -0700 (PDT) Received: from mail-da0-f50.google.com (mail-da0-f50.google.com [209.85.210.50]) by mx.google.com with ESMTPS id yl9si8392108pbc.2.2012.10.15.14.54.37 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Oct 2012 14:54:37 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of anton.vorontsov@linaro.org) client-ip=209.85.210.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of anton.vorontsov@linaro.org) smtp.mail=anton.vorontsov@linaro.org Received: by mail-da0-f50.google.com with SMTP id z20so3189820dae.37 for ; Mon, 15 Oct 2012 14:54:37 -0700 (PDT) Received: by 10.68.130.194 with SMTP id og2mr40834257pbb.131.1350338076697; Mon, 15 Oct 2012 14:54:36 -0700 (PDT) Received: from localhost (ip-64-134-230-8.public.wayport.net. [64.134.230.8]) by mx.google.com with ESMTPS id j9sm9668634paw.2.2012.10.15.14.54.35 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Oct 2012 14:54:36 -0700 (PDT) From: Anton Vorontsov To: Russell King Cc: John Stultz , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linaro-kernel@lists.linaro.org, patches@linaro.org, kernel-team@android.com, Ben Dooks , Kukjin Kim , Sascha Hauer , Tony Lindgren , Mark Brown , Liam Girdwood Subject: [PATCH 01/10] ARM: mach-rpc: Don't register FIQs with genirq Date: Mon, 15 Oct 2012 14:51:25 -0700 Message-Id: <1350337894-9744-1-git-send-email-anton.vorontsov@linaro.org> X-Mailer: git-send-email 1.7.12.3 In-Reply-To: <20121015214954.GA3352@lizard> References: <20121015214954.GA3352@lizard> X-Gm-Message-State: ALoCoQnKc3JpMfVhbHWIOvJbj2n9xp52Z7p/JT5SNkMaV1F2/3YSc4ESZ62VuSHDV7+W1G6PnaC6 mach-rps registers FIQ controller with genirq, which makes no sense: these FIQs cannot be routed to IRQs, so there is no need to register it with genirq. This effectively makes FIQ_START irrelevant. Signed-off-by: Anton Vorontsov --- arch/arm/mach-rpc/dma.c | 4 ++-- arch/arm/mach-rpc/include/mach/irqs.h | 5 +++++ arch/arm/mach-rpc/irq.c | 19 ++++--------------- 3 files changed, 11 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c index 85883b2..4a525be 100644 --- a/arch/arm/mach-rpc/dma.c +++ b/arch/arm/mach-rpc/dma.c @@ -289,13 +289,13 @@ static void floppy_enable_dma(unsigned int chan, dma_t *dma) set_fiq_handler(fiqhandler_start, fiqhandler_length); set_fiq_regs(®s); - enable_fiq(fdma->fiq); + iomd_unmask_fiq(fdma->fiq); } static void floppy_disable_dma(unsigned int chan, dma_t *dma) { struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma); - disable_fiq(fdma->fiq); + iomd_mask_fiq(fdma->fiq); release_fiq(&fh); } diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h index 6868e17..f27ead1 100644 --- a/arch/arm/mach-rpc/include/mach/irqs.h +++ b/arch/arm/mach-rpc/include/mach/irqs.h @@ -37,6 +37,11 @@ #define FIQ_EXPANSIONCARD 6 #define FIQ_FORCE 7 +#ifndef __ASSEMBLY__ +extern void iomd_mask_fiq(int fiq); +extern void iomd_unmask_fiq(int fiq); +#endif + /* * This is the offset of the FIQ "IRQ" numbers */ diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c index 3e4fa84..a4221b3 100644 --- a/arch/arm/mach-rpc/irq.c +++ b/arch/arm/mach-rpc/irq.c @@ -89,30 +89,24 @@ static struct irq_chip iomd_dma_chip = { .irq_unmask = iomd_unmask_irq_dma, }; -static void iomd_mask_irq_fiq(struct irq_data *d) +void iomd_mask_fiq(int fiq) { unsigned int val, mask; - mask = 1 << (d->irq & 7); + mask = 1 << (fiq & 7); val = iomd_readb(IOMD_FIQMASK); iomd_writeb(val & ~mask, IOMD_FIQMASK); } -static void iomd_unmask_irq_fiq(struct irq_data *d) +void iomd_unmask_fiq(int fiq) { unsigned int val, mask; - mask = 1 << (d->irq & 7); + mask = 1 << (fiq & 7); val = iomd_readb(IOMD_FIQMASK); iomd_writeb(val | mask, IOMD_FIQMASK); } -static struct irq_chip iomd_fiq_chip = { - .irq_ack = iomd_mask_irq_fiq, - .irq_mask = iomd_mask_irq_fiq, - .irq_unmask = iomd_unmask_irq_fiq, -}; - extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end; void __init rpc_init_irq(void) @@ -155,11 +149,6 @@ void __init rpc_init_irq(void) handle_level_irq); set_irq_flags(irq, flags); break; - - case 64 ... 71: - irq_set_chip(irq, &iomd_fiq_chip); - set_irq_flags(irq, IRQF_VALID); - break; } }