From patchwork Thu May 1 09:56:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 29445 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ie0-f200.google.com (mail-ie0-f200.google.com [209.85.223.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id C91C320B8D for ; Thu, 1 May 2014 09:57:12 +0000 (UTC) Received: by mail-ie0-f200.google.com with SMTP id lx4sf15395634iec.7 for ; Thu, 01 May 2014 02:57:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=O25We+b0p/gyaLXzArQREiTCdV8GAzVcMCABAhP3XOU=; b=QO3phyIeWONoKXzHKS915pSwzbNEoEimuxBuqlgakS+88qZD2PwnmPJ4FimojSw7RF qx+Ok8X6MwSAZUFWMYko3g2UNTjGzrF7T/98msH3/Ezrx6BVofQBD6kNDfdBrslWNXPI 4+Q22xh/f/Z2tx0EN5dB3jRZNGv/W8/ZY6D7FUWqM3ynxewm4dFCepJot8zbOmViiaIn ue8Q8uUphfX9U8P4AMIobFLWezk5NHdM6llgaDhjB60ervn5jngR3/Hqo9VIjHc3Do2o iLeDltBrfP6y1xo+ijDQ0Q6eavEauLnjNvSxSlrX5XlpuSRA6UbNjowYftUxF6fYF/jl ffvg== X-Gm-Message-State: ALoCoQkDhw73iAPxs3B5CQrL3yNSuz5RtTJEPmDpG9LTlTc9GPokj/yRTrNdfQz1O6eM6H6+BO+9 X-Received: by 10.42.223.10 with SMTP id ii10mr4520635icb.21.1398938232228; Thu, 01 May 2014 02:57:12 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.84.239 with SMTP id l102ls1043267qgd.81.gmail; Thu, 01 May 2014 02:57:12 -0700 (PDT) X-Received: by 10.220.167.2 with SMTP id o2mr8209915vcy.8.1398938232113; Thu, 01 May 2014 02:57:12 -0700 (PDT) Received: from mail-vc0-f179.google.com (mail-vc0-f179.google.com [209.85.220.179]) by mx.google.com with ESMTPS id tv3si5941072vdc.198.2014.05.01.02.57.12 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 01 May 2014 02:57:12 -0700 (PDT) Received-SPF: none (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) client-ip=209.85.220.179; Received: by mail-vc0-f179.google.com with SMTP id ij19so3653443vcb.38 for ; Thu, 01 May 2014 02:57:12 -0700 (PDT) X-Received: by 10.52.166.102 with SMTP id zf6mr6831518vdb.2.1398938232016; Thu, 01 May 2014 02:57:12 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp12880vcb; Thu, 1 May 2014 02:57:11 -0700 (PDT) X-Received: by 10.180.91.1 with SMTP id ca1mr1539727wib.32.1398938231138; Thu, 01 May 2014 02:57:11 -0700 (PDT) Received: from mail-we0-f171.google.com (mail-we0-f171.google.com [74.125.82.171]) by mx.google.com with ESMTPS id eb3si574107wib.59.2014.05.01.02.57.10 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 01 May 2014 02:57:11 -0700 (PDT) Received-SPF: none (google.com: lee.jones@linaro.org does not designate permitted sender hosts) client-ip=74.125.82.171; Received: by mail-we0-f171.google.com with SMTP id w62so2021372wes.16 for ; Thu, 01 May 2014 02:57:10 -0700 (PDT) X-Received: by 10.194.62.176 with SMTP id z16mr87527wjr.67.1398938230580; Thu, 01 May 2014 02:57:10 -0700 (PDT) Received: from lee--X1.home (host109-148-238-223.range109-148.btcentralplus.com. [109.148.238.223]) by mx.google.com with ESMTPSA id bj5sm2696494wib.3.2014.05.01.02.57.08 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 01 May 2014 02:57:09 -0700 (PDT) From: Lee Jones To: linux-kernel@vger.kernel.org Cc: computersforpeace@gmail.com, linux-mtd@lists.infradead.org, kernel@stlinux.com, Lee Jones , devicetree@vger.kernel.org Subject: [PATCH 02/47] mtd: nand: stm_nand_bch: provide Device Tree documentation Date: Thu, 1 May 2014 10:56:09 +0100 Message-Id: <1398938214-17847-3-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1398938214-17847-1-git-send-email-lee.jones@linaro.org> References: <1398938214-17847-1-git-send-email-lee.jones@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This is where we describe the different new and generic options used by the ST BCH driver. Cc: devicetree@vger.kernel.org Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mtd/stm-nand.txt | 123 +++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/stm-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/stm-nand.txt b/Documentation/devicetree/bindings/mtd/stm-nand.txt new file mode 100644 index 0000000..9f9325f --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/stm-nand.txt @@ -0,0 +1,123 @@ +STM BCH NAND Support +-------------------- + +Required properties: + +- compatible : Should be "st,nand-bch" +- reg : Should contain register's location and length +- reg-names : "nand_mem" - NAND Controller register map + "nand_dma" - BCH Controller DMA configuration map +- interrupts : Interrupt number +- interrupt-names : "nand_irq" - NAND Controller IRQ +- st,nand-banks : Subnode representing one or more "banks" of NAND + Flash, connected to an STM NAND Controller (see + description below). +- nand-ecc-strength : Generic NAND property (See mtd/nand.txt) +- st,bch-bitflip-threshold + : The threshold at which the number of corrected bit- + flips per sector is deemed to have reached an + excessive level (triggers '-EUCLEAN' to be returned + to the caller). The value should be in the range 1 + to where is 18 or 30, + depending on the BCH ECC mode in operation. A value + of 0, or if left unspecified, is interpreted by the + driver as . + +Properties describing Bank of NAND Flash ("st,nand-banks"): + +- st,nand-csn : Chip select associated with the Bank. +- st,nand-timing-spec : [Optional] NAND Device Timing Data. All times + expressed in ns, except where stated otherwise: + + tR : Max Page Read delay [us] + tCLS : Min CLE setup time + tCS : Min CE setup time + tALS : Min ALE setup time + tDS : Min Data setup time + tWP : Min WE pulse width + tCLH : Min CLE hold time + tCH : Min CE hold time + tALH : Min ALE hold time + tDH : Min Data hold time + tWB : Max WE high to busy + tWH : Min WE hold time + tWC : Min Write cycle time + tRP : Min RE pulse width + tREH : Min RE high hold time + tRC : Min Read cycle time + tREA : Max Read access time + tRHOH : Min RE high to output hold + tCEA : Max CE access time + tCOH : Min CE high to output hold + tCHZ : Max CE high to output high Z + tCSD : Min CE high to ALE/CLE don't care + +- st,nand-timing-relax : [Optional] Number of IP clock cycles by which to + "relax" timing configuration. Required on some boards + to accommodate board-level limitations. Applies to + 'st,nand-timing-spec' and ONFI timing mode + configuration. + +- nand-on-flash-bbt : Generic NAND property (See mtd/nand.txt) + +- partitions : [Optional] Subnode describing MTD partition map + (see mtd/partition.txt) + +Note, during initialisation, the NAND Controller timing registers are configured +according to one of the following methods, in order of precedence: + + 1. Configuration based on "st,nand_timing_spec" if supplied. + + 2. Configuration based on ONFI timing mode, as advertised by the + device during ONFI-probing (ONFI-compliant NAND only). + + 3. Use reset/safe timing values + +Example: + + nandbch: nand-bch { + compatible = "st,nand-bch"; + reg = <0xfe901000 0x1000>, <0xfef00800 0x0800>; + reg-names = "nand_mem", "nand_dma"; + interrupts = <0 139 0x0>; + interrupt-names = "nand_irq"; + nand-ecc-strength = <30>; + st,nand-banks = <&nand_banks>; + + status = "okay"; + }; + + nand_banks: nand-banks { + bank0 { + /* NAND_BBT_USE_FLASH */ + nand-on-flash-bbt; + st,nand-csn = <0>; + st,nand-timing-data = <&nand_timing0>; + + partitions { + #address-cells = <1>; + #size-cells = <1>; + + partition@0{ + label = "NAND Flash 1"; + reg = <0x00000000 0x00800000>; + }; + partition@800000{ + label = "NAND Flash 2"; + reg = <0x00800000 0x0F800000>; + }; + }; + }; + }; + + nand_timing0: nand-timing { + sig-setup = <10>; + sig-hold = <10>; + CE-deassert = <0>; + WE-to-RBn = <100>; + wr-on = <10>; + wr-off = <30>; + rd-on = <10>; + rd-off = <30>; + chip-delay = <30>; /* delay in us */ + };