From patchwork Thu May 1 09:56:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 29451 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pd0-f197.google.com (mail-pd0-f197.google.com [209.85.192.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1154A203F3 for ; Thu, 1 May 2014 09:57:24 +0000 (UTC) Received: by mail-pd0-f197.google.com with SMTP id g10sf2977411pdj.0 for ; Thu, 01 May 2014 02:57:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=rZZj8L083/Fv29XromlfXkMGJ6n4P+hfrDLxsDmQ8TU=; b=bpZbgsLVGiJ/Yr7XKnfer+PrUUNKzxnuitw6UDbjT84aofeDNwEvkQRnzqKAiJ05mh d+/sfijKu/zQvXwmHnetq5R1w29eoURbsyXuWxEu6gH1xJno2QsHkt8/guBuEmfpgz/7 K9+3eo4bYib/f4ff9qriTSaD0A/R3Ye/6sh+zRA2mLf2Enib+/9N7lNzrPRbpOyNDoPC NqdDTtvFaX6OJ16CxWOBJz5dk+H8sCzxWom8JXZ6URQmddjmyvhVLUQcPqEjsIFO3alo kEj56TlHRVtUDBygHAlv1N4bBBhtVVnW1ZoE/PlpuS4dJRRKxHPceFuX05UtVhARm2oM mcmw== X-Gm-Message-State: ALoCoQkkaGf6iVFHEVwTYmPBC9nkFJbx5ozgWsvFN1L4VcwH/HT8RdjWQkCEaP+fQLkSn7V2LeF+ X-Received: by 10.66.232.38 with SMTP id tl6mr5382297pac.33.1398938244169; Thu, 01 May 2014 02:57:24 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.83.115 with SMTP id i106ls968967qgd.97.gmail; Thu, 01 May 2014 02:57:24 -0700 (PDT) X-Received: by 10.220.159.4 with SMTP id h4mr8218152vcx.1.1398938244009; Thu, 01 May 2014 02:57:24 -0700 (PDT) Received: from mail-vc0-f175.google.com (mail-vc0-f175.google.com [209.85.220.175]) by mx.google.com with ESMTPS id f17si5974762vco.27.2014.05.01.02.57.23 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 01 May 2014 02:57:24 -0700 (PDT) Received-SPF: none (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) client-ip=209.85.220.175; Received: by mail-vc0-f175.google.com with SMTP id lh4so3630615vcb.20 for ; Thu, 01 May 2014 02:57:23 -0700 (PDT) X-Received: by 10.58.123.71 with SMTP id ly7mr8211619veb.11.1398938243933; Thu, 01 May 2014 02:57:23 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp12893vcb; Thu, 1 May 2014 02:57:23 -0700 (PDT) X-Received: by 10.180.36.66 with SMTP id o2mr1550300wij.40.1398938243002; Thu, 01 May 2014 02:57:23 -0700 (PDT) Received: from mail-we0-f178.google.com (mail-we0-f178.google.com [74.125.82.178]) by mx.google.com with ESMTPS id t9si564246wif.117.2014.05.01.02.57.22 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 01 May 2014 02:57:22 -0700 (PDT) Received-SPF: none (google.com: lee.jones@linaro.org does not designate permitted sender hosts) client-ip=74.125.82.178; Received: by mail-we0-f178.google.com with SMTP id u56so1977828wes.37 for ; Thu, 01 May 2014 02:57:22 -0700 (PDT) X-Received: by 10.180.207.10 with SMTP id ls10mr1557020wic.22.1398938242591; Thu, 01 May 2014 02:57:22 -0700 (PDT) Received: from lee--X1.home (host109-148-238-223.range109-148.btcentralplus.com. [109.148.238.223]) by mx.google.com with ESMTPSA id bj5sm2696494wib.3.2014.05.01.02.57.20 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 01 May 2014 02:57:21 -0700 (PDT) From: Lee Jones To: linux-kernel@vger.kernel.org Cc: computersforpeace@gmail.com, linux-mtd@lists.infradead.org, kernel@stlinux.com, Lee Jones Subject: [PATCH 08/47] mtd: nand: stm_nand_bch: initialise the BCH Controller Date: Thu, 1 May 2014 10:56:15 +0100 Message-Id: <1398938214-17847-9-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1398938214-17847-1-git-send-email-lee.jones@linaro.org> References: <1398938214-17847-1-git-send-email-lee.jones@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This call resets the ECC stats, boot-mode controller and the AFM (Advanced Flex Mode) controller, then enables Advanced Flex Mode, configures the DMA plugs and finally enables the NANDi controller IRQs. All required initialisation for clean running of the driver. Signed-off-by: Lee Jones --- drivers/mtd/nand/stm_nand_bch.c | 56 +++++++++++++++++++++++++++++++++++++++++ include/linux/mtd/stm_nand.h | 20 +++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/drivers/mtd/nand/stm_nand_bch.c b/drivers/mtd/nand/stm_nand_bch.c index d73568c..62a41de 100644 --- a/drivers/mtd/nand/stm_nand_bch.c +++ b/drivers/mtd/nand/stm_nand_bch.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -269,6 +270,56 @@ static void nandi_disable_interrupts(struct nandi_controller *nandi, writel(val, nandi->base + NANDBCH_INT_EN); } +static void nandi_init_bch(struct nandi_controller *nandi, int emi_bank) +{ + dev_dbg(nandi->dev, "%s\n", __func__); + + /* Initialise BCH Controller */ + emiss_nandi_select(STM_NANDI_BCH); + + /* Reset and disable boot-mode controller */ + writel(BOOT_CFG_RESET, nandi->base + NANDBCH_BOOTBANK_CFG); + udelay(1); + writel(0x00000000, nandi->base + NANDBCH_BOOTBANK_CFG); + + /* Reset AFM controller */ + writel(CFG_RESET, nandi->base + NANDBCH_CONTROLLER_CFG); + udelay(1); + writel(0x00000000, nandi->base + NANDBCH_CONTROLLER_CFG); + + /* Set EMI Bank */ + writel(0x1 << emi_bank, nandi->base + NANDBCH_FLEX_MUXCTRL); + + /* Reset ECC stats */ + writel(CFG_RESET_ECC_ALL, nandi->base + NANDBCH_CONTROLLER_CFG); + udelay(1); + + /* Enable AFM */ + writel(CFG_ENABLE_AFM, nandi->base + NANDBCH_CONTROLLER_CFG); + + /* Configure Read DMA Plugs (values supplied by Validation) */ + writel(0x00000005, nandi->dma + EMISS_NAND_RD_DMA_PAGE_SIZE); + writel(0x00000005, nandi->dma + EMISS_NAND_RD_DMA_MAX_OPCODE_SIZE); + writel(0x00000002, nandi->dma + EMISS_NAND_RD_DMA_MIN_OPCODE_SIZE); + writel(0x00000001, nandi->dma + EMISS_NAND_RD_DMA_MAX_CHUNK_SIZE); + writel(0x00000000, nandi->dma + EMISS_NAND_RD_DMA_MAX_MESSAGE_SIZE); + + /* Configure Write DMA Plugs (values supplied by Validation) */ + writel(0x00000005, nandi->dma + EMISS_NAND_WR_DMA_PAGE_SIZE); + writel(0x00000005, nandi->dma + EMISS_NAND_WR_DMA_MAX_OPCODE_SIZE); + writel(0x00000002, nandi->dma + EMISS_NAND_WR_DMA_MIN_OPCODE_SIZE); + writel(0x00000001, nandi->dma + EMISS_NAND_WR_DMA_MAX_CHUNK_SIZE); + writel(0x00000000, nandi->dma + EMISS_NAND_WR_DMA_MAX_MESSAGE_SIZE); + + nandi_enable_interrupts(nandi, NAND_INT_ENABLE); +} + +static void nandi_init_controller(struct nandi_controller *nandi, + int emi_bank) +{ + nandi_init_bch(nandi, emi_bank); +} + static int remap_named_resource(struct platform_device *pdev, char *name, void __iomem **io_ptr) @@ -341,6 +392,7 @@ nandi_init_resources(struct platform_device *pdev) static int stm_nand_bch_probe(struct platform_device *pdev) { struct stm_plat_nand_bch_data *pdata = pdev->dev.platform_data; + struct stm_nand_bank_data *bank; struct nandi_controller *nandi; nandi = nandi_init_resources(pdev); @@ -352,6 +404,10 @@ static int stm_nand_bch_probe(struct platform_device *pdev) init_completion(&nandi->seq_completed); init_completion(&nandi->rbn_completed); + bank = pdata->bank; + if (bank) + nandi_init_controller(nandi, bank->csn); + return 0; } diff --git a/include/linux/mtd/stm_nand.h b/include/linux/mtd/stm_nand.h index da2006c..99a69ca 100644 --- a/include/linux/mtd/stm_nand.h +++ b/include/linux/mtd/stm_nand.h @@ -17,6 +17,26 @@ #include +/* + * Board-level specification relating to a 'bank' of NAND Flash + */ +struct stm_nand_bank_data { + int csn; + int nr_partitions; + struct mtd_partition *partitions; + unsigned int options; + unsigned int bbt_options; + + struct nand_timing_spec *timing_spec; + + /* + * No. of IP clk cycles by which to 'relax' the timing configuration. + * Required on some boards to to accommodate board-level limitations. + * Used in conjunction with 'nand_timing_spec' and ONFI configuration. + */ + int timing_relax; +}; + struct stm_plat_nand_bch_data { struct stm_nand_bank_data *bank; enum stm_nand_bch_ecc_config bch_ecc_cfg;