From patchwork Fri May 23 10:31:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 30692 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pa0-f71.google.com (mail-pa0-f71.google.com [209.85.220.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 200BC20369 for ; Fri, 23 May 2014 10:32:42 +0000 (UTC) Received: by mail-pa0-f71.google.com with SMTP id kq14sf17150103pab.6 for ; Fri, 23 May 2014 03:32:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=7G6mAXAf8GnEQ6LDsysMj/aPwK3XZILdt2CQE0GBx7Q=; b=R+Hac+zKLbOhhylWT+5463GxS8PcNrRsQEgzS6O8gjmhYgALayAznMvDiUHGztpl/O StkzSUvBj4LdeDhtTaegaGVbgiraIWVrEqJlDH5GZZAu6OGdHlI3dzgxzzrRfVeXUSsx oUl4Hjx8mllAn2V4wVSo95UNEaVN17mVir5zMAY+TK0i3ERij71Eb5RP30bumjGwFY2I vVmIKNsHhl/AJtwnfTCWN8gZ6aGX4LWGMMaHivfuK+owv1sHw0FaPltW6yIuNdXL+oXo xzKVQWbqGrz4P90VnRjPKHAEgjtPdqmGMHG43bR3N58piXxnl7sg1TFWZzDKEWLChc2H WJiA== X-Gm-Message-State: ALoCoQnLERMKr2dj1x9xl7TFbZr8Za/oCbVAcS+TktbhSgNdje6P2p+nHVE1qN0Mku9bmeJxES72 X-Received: by 10.66.222.129 with SMTP id qm1mr1787057pac.6.1400841161406; Fri, 23 May 2014 03:32:41 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.88.5 with SMTP id s5ls1695979qgd.75.gmail; Fri, 23 May 2014 03:32:41 -0700 (PDT) X-Received: by 10.220.12.66 with SMTP id w2mr3345205vcw.15.1400841161296; Fri, 23 May 2014 03:32:41 -0700 (PDT) Received: from mail-vc0-f179.google.com (mail-vc0-f179.google.com [209.85.220.179]) by mx.google.com with ESMTPS id u17si1377485vew.74.2014.05.23.03.32.41 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 23 May 2014 03:32:41 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.179 as permitted sender) client-ip=209.85.220.179; Received: by mail-vc0-f179.google.com with SMTP id im17so5977982vcb.38 for ; Fri, 23 May 2014 03:32:41 -0700 (PDT) X-Received: by 10.220.249.198 with SMTP id ml6mr642464vcb.36.1400841161166; Fri, 23 May 2014 03:32:41 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp19796vcb; Fri, 23 May 2014 03:32:40 -0700 (PDT) X-Received: by 10.68.193.166 with SMTP id hp6mr4664796pbc.144.1400841160248; Fri, 23 May 2014 03:32:40 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bg4si3275525pbb.67.2014.05.23.03.32.39 for ; Fri, 23 May 2014 03:32:39 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752757AbaEWKcN (ORCPT + 27 others); Fri, 23 May 2014 06:32:13 -0400 Received: from mail-wi0-f172.google.com ([209.85.212.172]:42523 "EHLO mail-wi0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752730AbaEWKcK (ORCPT ); Fri, 23 May 2014 06:32:10 -0400 Received: by mail-wi0-f172.google.com with SMTP id hi2so601093wib.17 for ; Fri, 23 May 2014 03:32:09 -0700 (PDT) X-Received: by 10.180.182.19 with SMTP id ea19mr2529742wic.14.1400841129432; Fri, 23 May 2014 03:32:09 -0700 (PDT) Received: from localhost.localdomain (AToulouse-654-1-404-187.w82-125.abo.wanadoo.fr. [82.125.3.187]) by mx.google.com with ESMTPSA id s9sm2200908wix.13.2014.05.23.03.32.08 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 23 May 2014 03:32:08 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, mingo@kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 27/71] clocksource: sh_tmu: Add index to struct sh_tmu_channel Date: Fri, 23 May 2014 12:31:07 +0200 Message-Id: <1400841111-6683-27-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1400841111-6683-1-git-send-email-daniel.lezcano@linaro.org> References: <537F214C.8000700@linaro.org> <1400841111-6683-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.lezcano@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Laurent Pinchart Use the index as the timer start/stop bit and when printing messages to identify the channel. Signed-off-by: Laurent Pinchart --- drivers/clocksource/sh_tmu.c | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c index a464ed8..e304304 100644 --- a/drivers/clocksource/sh_tmu.c +++ b/drivers/clocksource/sh_tmu.c @@ -39,6 +39,7 @@ struct sh_tmu_device; struct sh_tmu_channel { struct sh_tmu_device *tmu; + unsigned int index; void __iomem *base; int irq; @@ -102,7 +103,6 @@ static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr, static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start) { - struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data; unsigned long flags, value; /* start stop register shared by multiple timer channels */ @@ -110,9 +110,9 @@ static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start) value = sh_tmu_read(ch, TSTR); if (start) - value |= 1 << cfg->timer_bit; + value |= 1 << ch->index; else - value &= ~(1 << cfg->timer_bit); + value &= ~(1 << ch->index); sh_tmu_write(ch, TSTR, value); raw_spin_unlock_irqrestore(&sh_tmu_lock, flags); @@ -125,7 +125,8 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch) /* enable clock */ ret = clk_enable(ch->tmu->clk); if (ret) { - dev_err(&ch->tmu->pdev->dev, "cannot enable clock\n"); + dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n", + ch->index); return ret; } @@ -303,7 +304,8 @@ static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, cs->mask = CLOCKSOURCE_MASK(32); cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; - dev_info(&ch->tmu->pdev->dev, "used as clock source\n"); + dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n", + ch->index); /* Register with dummy 1 Hz value, gets updated in ->enable() */ clocksource_register_hz(cs, 1); @@ -349,12 +351,12 @@ static void sh_tmu_clock_event_mode(enum clock_event_mode mode, switch (mode) { case CLOCK_EVT_MODE_PERIODIC: dev_info(&ch->tmu->pdev->dev, - "used for periodic clock events\n"); + "ch%u: used for periodic clock events\n", ch->index); sh_tmu_clock_event_start(ch, 1); break; case CLOCK_EVT_MODE_ONESHOT: dev_info(&ch->tmu->pdev->dev, - "used for oneshot clock events\n"); + "ch%u: used for oneshot clock events\n", ch->index); sh_tmu_clock_event_start(ch, 0); break; case CLOCK_EVT_MODE_UNUSED: @@ -407,7 +409,8 @@ static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, ced->suspend = sh_tmu_clock_event_suspend; ced->resume = sh_tmu_clock_event_resume; - dev_info(&ch->tmu->pdev->dev, "used for clock events\n"); + dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n", + ch->index); clockevents_config_and_register(ced, 1, 0x300, 0xffffffff); @@ -415,8 +418,8 @@ static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, dev_name(&ch->tmu->pdev->dev), ch); if (ret) { - dev_err(&ch->tmu->pdev->dev, "failed to request irq %d\n", - ch->irq); + dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n", + ch->index, ch->irq); return; } } @@ -441,9 +444,19 @@ static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, memset(ch, 0, sizeof(*ch)); ch->tmu = tmu; + /* + * The SH3 variant (SH770x, SH7705, SH7710 and SH7720) maps channel + * registers blocks at base + 2 + 12 * index, while all other variants + * map them at base + 4 + 12 * index. We can compute the index by just + * dividing by 12, the 2 bytes or 4 bytes offset being hidden by the + * integer division. + */ + ch->index = cfg->channel_offset / 12; + ch->irq = platform_get_irq(tmu->pdev, 0); if (ch->irq < 0) { - dev_err(&tmu->pdev->dev, "failed to get irq\n"); + dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n", + ch->index); return ch->irq; }