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[209.132.180.67]) by mx.google.com with ESMTP id br6si858821pdb.483.2014.07.03.07.29.19; Thu, 03 Jul 2014 07:29:19 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965024AbaGCO3I (ORCPT + 27 others); Thu, 3 Jul 2014 10:29:08 -0400 Received: from mail-pd0-f174.google.com ([209.85.192.174]:63793 "EHLO mail-pd0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965005AbaGCO3D (ORCPT ); Thu, 3 Jul 2014 10:29:03 -0400 Received: by mail-pd0-f174.google.com with SMTP id y10so306764pdj.5 for ; Thu, 03 Jul 2014 07:29:02 -0700 (PDT) X-Received: by 10.70.91.195 with SMTP id cg3mr4427708pdb.73.1404397742028; Thu, 03 Jul 2014 07:29:02 -0700 (PDT) Received: from localhost.localdomain ([60.166.214.87]) by mx.google.com with ESMTPSA id ph6sm29283731pbc.38.2014.07.03.07.28.53 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 03 Jul 2014 07:29:01 -0700 (PDT) From: Zhangfei Gao To: Kishon Vijay Abraham I , arnd@arndb.de, mark.rutland@arm.com, haifeng.yan@linaro.org, jchxue@gmail.com, zhangfei.gao@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Jiancheng Xue Subject: [PATCH v3 1/2] Documentation: Document Hisilicon hix5hd2 sata PHY Date: Thu, 3 Jul 2014 22:28:37 +0800 Message-Id: <1404397718-11495-2-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1404397718-11495-1-git-send-email-zhangfei.gao@linaro.org> References: <1404397718-11495-1-git-send-email-zhangfei.gao@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: zhangfei.gao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.177 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Jiancheng Xue Add necessary binding documentation SATA PHY on Hisilicon hix5hd2 soc. Signed-off-by: Jiancheng Xue Signed-off-by: Zhangfei Gao --- .../devicetree/bindings/phy/hix5hd2-phy.txt | 22 ++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/hix5hd2-phy.txt diff --git a/Documentation/devicetree/bindings/phy/hix5hd2-phy.txt b/Documentation/devicetree/bindings/phy/hix5hd2-phy.txt new file mode 100644 index 0000000..296168b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hix5hd2-phy.txt @@ -0,0 +1,22 @@ +Hisilicon hix5hd2 SATA PHY +----------------------- + +Required properties: +- compatible: should be "hisilicon,hix5hd2-sata-phy" +- reg: offset and length of the PHY registers +- #phy-cells: must be 0 +Refer to phy/phy-bindings.txt for the generic PHY binding properties + +Optional Properties: +- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral. +- hisilicon,power-reg: offset and bit number within peripheral-syscon, + register of controlling sata power supply. + +Example: + sata_phy: phy@f9900000 { + compatible = "hisilicon,hix5hd2-sata-phy"; + reg = <0xf9900000 0x10000>; + #phy-cells = <0>; + hisilicon,peripheral-syscon = <&peripheral_ctrl>; + hisilicon,power-reg = <0x8 10>; + };