From patchwork Mon Jul 14 10:42:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 33570 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f71.google.com (mail-oa0-f71.google.com [209.85.219.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 5C1722061E for ; Mon, 14 Jul 2014 10:44:04 +0000 (UTC) Received: by mail-oa0-f71.google.com with SMTP id g18sf23169082oah.2 for ; Mon, 14 Jul 2014 03:44:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe:content-type; bh=myOn6aJJ5gjE51r+tBQe1QC8O1G3JXe9oZWGNjDqvz4=; b=Ha3cpeqJ8NCZ4iRncf+T3XqoXQfLIqV+EZ5vVdPnh5LnxMx8p+bLvl0WttjEjb0gUr woZ9ZR8OFKCyVX8KldmGiTRPwLtTFKTI6mCJwXkdRvhDNO00/DOX/PJJv9NEfUfMUcUE op9k8hB1ngr0cxPCKuF18eIPFMjaSF3t1/IR/gXOU2bdnCruFCvReoR5PpSaxuItFj0Q puZdtKYV2rShQRKJawJQNYanrMVpYFEo8rpyCgrTeZ/8po5V6tWAJ598/6sEuXmrBxqo apnLd/ERcep6wTY7gHopcTjhB9ZJy2KrJV4HV9n3k24dlrddJ3j2ShfWUG8cq7dL8YLR XsJw== X-Gm-Message-State: ALoCoQmebAyke9M3PicEj/TYKSR3+ko+XkNjgezxT3rwFxM0WfZ4vl6Wpn4wgHxNXgoKnoa0czhI X-Received: by 10.182.43.196 with SMTP id y4mr7095505obl.35.1405334644018; Mon, 14 Jul 2014 03:44:04 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.29.195 with SMTP id b61ls1021653qgb.50.gmail; Mon, 14 Jul 2014 03:44:03 -0700 (PDT) X-Received: by 10.220.250.203 with SMTP id mp11mr15595873vcb.2.1405334643126; Mon, 14 Jul 2014 03:44:03 -0700 (PDT) Received: from mail-vc0-f171.google.com (mail-vc0-f171.google.com [209.85.220.171]) by mx.google.com with ESMTPS id bw1si5222554vcb.18.2014.07.14.03.44.03 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 14 Jul 2014 03:44:03 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.171 as permitted sender) client-ip=209.85.220.171; Received: by mail-vc0-f171.google.com with SMTP id id10so6761055vcb.2 for ; Mon, 14 Jul 2014 03:44:03 -0700 (PDT) X-Received: by 10.58.8.12 with SMTP id n12mr1498812vea.28.1405334643043; Mon, 14 Jul 2014 03:44:03 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp124877vcb; Mon, 14 Jul 2014 03:44:02 -0700 (PDT) X-Received: by 10.70.54.135 with SMTP id j7mr15993721pdp.94.1405334641272; Mon, 14 Jul 2014 03:44:01 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bi15si4435367pdb.419.2014.07.14.03.44.00; Mon, 14 Jul 2014 03:44:00 -0700 (PDT) Received-SPF: none (google.com: linux-omap-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754562AbaGNKn7 (ORCPT + 6 others); Mon, 14 Jul 2014 06:43:59 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:60785 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754218AbaGNKng (ORCPT ); Mon, 14 Jul 2014 06:43:36 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6EAh7No022820; Mon, 14 Jul 2014 05:43:07 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6EAh7he012807; Mon, 14 Jul 2014 05:43:07 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Mon, 14 Jul 2014 05:43:07 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6EAgdF2003492; Mon, 14 Jul 2014 05:43:04 -0500 From: Kishon Vijay Abraham I To: , , , , CC: , Rob Herring , Pawel Moll , Mark Rutland , Kumar Gala Subject: [RESEND PATCH 7/8] ARM: dts: dra7: Add dt data for PCIe PHY Date: Mon, 14 Jul 2014 16:12:22 +0530 Message-ID: <1405334543-25509-8-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1405334543-25509-1-git-send-email-kishon@ti.com> References: <1405334543-25509-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: kishon@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Added dt data for PCIe PHY as a child node of ocp2scp3. The documention for this node can be found @ ../bindings/phy/ti-phy.txt. 26.3.3 PCIe Shared PHY Subsystem Integration in vE of DRA7xx ES1.0 describes the PCIe PHY subsystem-related components integrated in the device. Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7.dtsi | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index e4999e4..cbaf47d 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -816,6 +816,47 @@ clock-names = "sysclk"; #phy-cells = <0>; }; + + pcie1_phy: pciephy@4a094000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x4a094000 0x80>, /* phy_rx */ + <0x4a094400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + ctrl-module = <&omap_control_pcie1phy>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&optfclk_pciephy1_32khz>, + <&optfclk_pciephy1_clk>, + <&optfclk_pciephy1_div_clk>, + <&optfclk_pciephy_div>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div"; + #phy-cells = <0>; + id = <1>; + ti,hwmods = "pcie1-phy"; + }; + + pcie2_phy: pciephy@4a095000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x4a095000 0x80>, /* phy_rx */ + <0x4a095400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + ctrl-module = <&omap_control_pcie2phy>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&optfclk_pciephy2_32khz>, + <&optfclk_pciephy2_clk>, + <&optfclk_pciephy2_div_clk>, + <&optfclk_pciephy_div>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div"; + #phy-cells = <0>; + ti,hwmods = "pcie2-phy"; + id = <2>; + status = "disabled"; + }; }; sata: sata@4a141100 {