From patchwork Wed Oct 15 03:07:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: wangyijing X-Patchwork-Id: 38756 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f198.google.com (mail-wi0-f198.google.com [209.85.212.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 7565C20973 for ; Wed, 15 Oct 2014 02:34:06 +0000 (UTC) Received: by mail-wi0-f198.google.com with SMTP id hi2sf272945wib.1 for ; Tue, 14 Oct 2014 19:34:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe:content-type; bh=/MWGcO43Hha6SAr1XYdXCEaT0a1HLH13yUc7NJtgAOU=; b=H1h+YEiPuYbnYFxQYvv1DOvWQE7xaC11C8uz9EaOM+6PqJPN6iwCBOzWdLlvDWF2D/ srAUY1UfzQAh9cVyuYiE4w4eKS5uNnOShhas4IQnSFFLk5IIAJU3rhcYrUMj+Mrr3yzr F/7xY3zyw0+Ff0V7HgUPh4J9MJsRnDqo0blnadVAvuyc86tMzm/frrnSFbTQcipMjS9Q iKPsjJHLYo6tEVaVqBExaIVLrZMmjnwqaAMGTtcHQicYnFNj025w4KhxT8l7KhQZamqS dHDc6THxXrVf9rzy0uauFjvcNaj3CKl4yd+HpgCmAnyCFZ5dY4zbfKe9euFdn0NIxRyh 3vHw== X-Gm-Message-State: ALoCoQmf5rk7J0QUguK/y06/zOtZQllxFoEIvFcp5KTxUvJpO0p2xvAH0kGLbEcg6Rsg1pwbXLul X-Received: by 10.112.141.230 with SMTP id rr6mr1535019lbb.4.1413340445644; Tue, 14 Oct 2014 19:34:05 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.21.41 with SMTP id s9ls9100lae.41.gmail; Tue, 14 Oct 2014 19:34:04 -0700 (PDT) X-Received: by 10.112.200.34 with SMTP id jp2mr9202465lbc.1.1413340444887; Tue, 14 Oct 2014 19:34:04 -0700 (PDT) Received: from mail-la0-f45.google.com (mail-la0-f45.google.com [209.85.215.45]) by mx.google.com with ESMTPS id an4si28699173lbc.47.2014.10.14.19.34.04 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 14 Oct 2014 19:34:04 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) client-ip=209.85.215.45; Received: by mail-la0-f45.google.com with SMTP id q1so263385lam.4 for ; Tue, 14 Oct 2014 19:34:04 -0700 (PDT) X-Received: by 10.112.167.130 with SMTP id zo2mr9307131lbb.4.1413340444473; Tue, 14 Oct 2014 19:34:04 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.84.229 with SMTP id c5csp517912lbz; Tue, 14 Oct 2014 19:34:03 -0700 (PDT) X-Received: by 10.68.102.100 with SMTP id fn4mr9622680pbb.48.1413340442825; Tue, 14 Oct 2014 19:34:02 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ks5si14586556pdb.42.2014.10.14.19.34.02 for ; Tue, 14 Oct 2014 19:34:02 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932877AbaJOCd7 (ORCPT + 27 others); Tue, 14 Oct 2014 22:33:59 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:39377 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932681AbaJOCZr (ORCPT ); Tue, 14 Oct 2014 22:25:47 -0400 Received: from 172.24.2.119 (EHLO szxeml412-hub.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CAT35381; Wed, 15 Oct 2014 10:25:43 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml412-hub.china.huawei.com (10.82.67.91) with Microsoft SMTP Server id 14.3.158.1; Wed, 15 Oct 2014 10:25:34 +0800 From: Yijing Wang To: Bjorn Helgaas CC: , , Xinwei Hu , Wuyun , , Russell King , , , , , Arnd Bergmann , Thomas Gleixner , "Konrad Rzeszutek Wilk" , , Joerg Roedel , , , Benjamin Herrenschmidt , , , Sebastian Ott , "Tony Luck" , , "David S. Miller" , , Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , "Sergei Shtylyov" , Michael Ellerman , Thierry Reding , "Thomas Petazzoni" , Liviu Dudau , Yijing Wang Subject: [PATCH v3 13/27] x86/xen/MSI: Use MSI chip framework to configure MSI/MSI-X irq Date: Wed, 15 Oct 2014 11:07:01 +0800 Message-ID: <1413342435-7876-14-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1413342435-7876-1-git-send-email-wangyijing@huawei.com> References: <1413342435-7876-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: wangyijing@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Use MSI chip framework instead of arch MSI functions to configure MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework. Signed-off-by: Yijing Wang Acked-by: David Vrabel CC: Konrad Rzeszutek Wilk --- arch/x86/pci/xen.c | 58 +++++++++++++++++++++++++++++++++++----------------- 1 files changed, 39 insertions(+), 19 deletions(-) diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c index e5b8b78..75067ca 100644 --- a/arch/x86/pci/xen.c +++ b/arch/x86/pci/xen.c @@ -157,7 +157,8 @@ static int acpi_register_gsi_xen(struct device *dev, u32 gsi, struct xen_pci_frontend_ops *xen_pci_frontend; EXPORT_SYMBOL_GPL(xen_pci_frontend); -static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +static int xen_setup_msi_irqs(struct msi_chip *chip, + struct pci_dev *dev, int nvec, int type) { int irq, ret, i; struct msi_desc *msidesc; @@ -219,7 +220,8 @@ static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq, msg->data = XEN_PIRQ_MSI_DATA; } -static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +static int xen_hvm_setup_msi_irqs(struct msi_chip *chip, + struct pci_dev *dev, int nvec, int type) { int irq, pirq; struct msi_desc *msidesc; @@ -267,7 +269,8 @@ error: #ifdef CONFIG_XEN_DOM0 static bool __read_mostly pci_seg_supported = true; -static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +static int xen_initdom_setup_msi_irqs(struct msi_chip *chip, + struct pci_dev *dev, int nvec, int type) { int ret = 0; struct msi_desc *msidesc; @@ -349,7 +352,8 @@ out: return ret; } -static void xen_initdom_restore_msi_irqs(struct pci_dev *dev) +static void xen_initdom_restore_msi_irqs(struct msi_chip *chip, + struct pci_dev *dev) { int ret = 0; @@ -376,7 +380,13 @@ static void xen_initdom_restore_msi_irqs(struct pci_dev *dev) } #endif -static void xen_teardown_msi_irqs(struct pci_dev *dev) +static void xen_teardown_msi_irq(struct msi_chip *chip, unsigned int irq) +{ + xen_destroy_irq(irq); +} + +static void xen_teardown_msi_irqs(struct msi_chip *chip, + struct pci_dev *dev) { struct msi_desc *msidesc; @@ -386,14 +396,22 @@ static void xen_teardown_msi_irqs(struct pci_dev *dev) else xen_pci_frontend_disable_msi(dev); - /* Free the IRQ's and the msidesc using the generic code. */ - default_teardown_msi_irqs(dev); -} + list_for_each_entry(msidesc, &dev->msi_list, list) { + int i, nvec; + if (msidesc->irq == 0) + continue; + if (msidesc->nvec_used) + nvec = msidesc->nvec_used; + else + nvec = 1 << msidesc->msi_attrib.multiple; + for (i = 0; i < nvec; i++) + xen_teardown_msi_irq(chip, msidesc->irq + i); + } -static void xen_teardown_msi_irq(unsigned int irq) -{ - xen_destroy_irq(irq); } + +struct msi_chip xen_msi_chip; + #endif int __init pci_xen_init(void) @@ -414,9 +432,9 @@ int __init pci_xen_init(void) #endif #ifdef CONFIG_PCI_MSI - x86_msi.setup_msi_irqs = xen_setup_msi_irqs; - x86_msi.teardown_msi_irq = xen_teardown_msi_irq; - x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs; + xen_msi_chip.setup_irqs = xen_setup_msi_irqs; + xen_msi_chip.teardown_irqs = xen_teardown_msi_irqs; + x86_msi_chip = &xen_msi_chip; pci_msi_ignore_mask = 1; #endif return 0; @@ -436,8 +454,9 @@ int __init pci_xen_hvm_init(void) #endif #ifdef CONFIG_PCI_MSI - x86_msi.setup_msi_irqs = xen_hvm_setup_msi_irqs; - x86_msi.teardown_msi_irq = xen_teardown_msi_irq; + xen_msi_chip.setup_irqs = xen_hvm_setup_msi_irqs; + xen_msi_chip.teardown_irq = xen_teardown_msi_irq; + x86_msi_chip = &xen_msi_chip; #endif return 0; } @@ -494,9 +513,10 @@ int __init pci_xen_initial_domain(void) int irq; #ifdef CONFIG_PCI_MSI - x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs; - x86_msi.teardown_msi_irq = xen_teardown_msi_irq; - x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs; + xen_msi_chip.setup_irqs = xen_initdom_setup_msi_irqs; + xen_msi_chip.teardown_irq = xen_teardown_msi_irq; + xen_msi_chip.restore_irqs = xen_initdom_restore_msi_irqs; + x86_msi_chip = &xen_msi_chip; pci_msi_ignore_mask = 1; #endif xen_setup_acpi_sci();