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[209.132.180.67]) by mx.google.com with ESMTP id ro9si9843949pab.72.2014.10.27.00.10.44 for ; Mon, 27 Oct 2014 00:10:44 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752689AbaJ0HKk (ORCPT + 26 others); Mon, 27 Oct 2014 03:10:40 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:10248 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752173AbaJ0HIU (ORCPT ); Mon, 27 Oct 2014 03:08:20 -0400 Received: from 172.24.2.119 (EHLO szxeml409-hub.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CBJ05365; Mon, 27 Oct 2014 15:07:32 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml409-hub.china.huawei.com (10.82.67.136) with Microsoft SMTP Server id 14.3.158.1; Mon, 27 Oct 2014 15:07:20 +0800 From: Yijing Wang To: Bjorn Helgaas CC: , , Xinwei Hu , Wuyun , , Russell King , Thomas Gleixner , "Thierry Reding" , Thomas Petazzoni , Yijing Wang Subject: [PATCH 03/10] arm/MSI: Save MSI controller in pci_sys_data Date: Mon, 27 Oct 2014 15:48:40 +0800 Message-ID: <1414396127-30023-4-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1414396127-30023-1-git-send-email-wangyijing@huawei.com> References: <1414396127-30023-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: wangyijing@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.51 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Saving msi controller in pci_sys_data make PCI bus and devices don't need to know msi controller details. It also make PCI enumeration code be decoupled from msi controller. Currently, we associate msi controller and PCI bus by adding .add_bus() in PCI host drivers, and assign parent PCI bus's msi controller to child bus in pci_alloc_child_bus(). In fact, all PCI devices under the same PCI host bridge share same msi controller. So msi controller should be seen as one of resources or attributes to be initialized in pci host bridge driver. Currently, pci hostbridge drivers create pci_host_bridge in pci_create_root_bus(), and pass arch specific pci sysdata to core pci scan functions. So pci arch sysdata is good place to save msi controller. But this is not the best solution, because we have to add arch spec pcibios_msi_controller() to extract out msi_controller from PCI sysdata. A better approach is to make a generic pci_host_bridge, save common info like msi controller, PCI domain, PCI hostbridge resources into it, and pass the generic pci_host_bridge to PCI scan functions. Then we can remove lots of arch spec functions. But these changes are huge, so we plan to do it in another series. Signed-off-by: Yijing Wang --- arch/arm/include/asm/mach/pci.h | 6 ++++++ arch/arm/kernel/bios32.c | 12 ++++++++++++ 2 files changed, 18 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 7fc4278..8144d61 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -22,6 +22,9 @@ struct hw_pci { #ifdef CONFIG_PCI_DOMAINS int domain; #endif +#ifdef CONFIG_PCI_MSI + struct msi_controller *msi_ctrl; +#endif struct pci_ops *ops; int nr_controllers; void **private_data; @@ -47,6 +50,9 @@ struct pci_sys_data { #ifdef CONFIG_PCI_DOMAINS int domain; #endif +#ifdef CONFIG_PCI_MSI + struct msi_controller *msi_ctrl; +#endif struct list_head node; int busnr; /* primary bus number */ u64 mem_offset; /* bus->cpu memory mapping offset */ diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 17a26c1..073229f 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -18,6 +18,15 @@ static int debug_pci; +#ifdef CONFIG_PCI_MSI +struct msi_controller *pcibios_msi_controller(struct pci_bus *bus) +{ + struct pci_sys_data *sysdata = bus->sysdata; + + return sysdata->msi_ctrl; +} +#endif + /* * We can't use pci_get_device() here since we are * called from interrupt context. @@ -471,6 +480,9 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, #ifdef CONFIG_PCI_DOMAINS sys->domain = hw->domain; #endif +#ifdef CONFIG_PCI_MSI + sys->msi_ctrl = hw->msi_ctrl; +#endif sys->busnr = busnr; sys->swizzle = hw->swizzle; sys->map_irq = hw->map_irq;