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[209.132.180.67]) by mx.google.com with ESMTP id rg11si10235215pdb.142.2014.10.27.04.07.39 for ; Mon, 27 Oct 2014 04:07:41 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752624AbaJ0LHh (ORCPT + 26 others); Mon, 27 Oct 2014 07:07:37 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:31377 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751191AbaJ0LGD (ORCPT ); Mon, 27 Oct 2014 07:06:03 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NE300J0AOASJV20@mailout3.w1.samsung.com>; Mon, 27 Oct 2014 11:08:52 +0000 (GMT) X-AuditID: cbfec7f5-b7f956d000005ed7-00-544e2718f2c2 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 97.B8.24279.8172E445; Mon, 27 Oct 2014 11:06:00 +0000 (GMT) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0NE300JBOO5RPJ10@eusync2.samsung.com>; Mon, 27 Oct 2014 11:06:00 +0000 (GMT) From: Marek Szyprowski To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Tomasz Figa , Kyungmin Park , Russell King - ARM Linux , Kukjin Kim , lauraa@codeaurora.org, linux-omap@vger.kernel.org, linus.walleij@linaro.org, santosh.shilimkar@ti.com, tony@atomide.com, drake@endlessm.com, loeliger@gmail.com, Mark Rutland Subject: [PATCH v6 7/7] ARM: dts: exynos4: Add nodes for L2 cache controller Date: Mon, 27 Oct 2014 12:05:50 +0100 Message-id: <1414407950-3029-8-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 In-reply-to: <1414407950-3029-1-git-send-email-m.szyprowski@samsung.com> References: <1414407950-3029-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrDLMWRmVeSWpSXmKPExsVy+t/xK7oS6n4hBqumCls8mv+Y2aJ3wVU2 i7NNb9gttnfOYLeY8mc5k8Wmx9dYLS7vmsNmMXtJP4vFjPP7mCxuX+a1OLd9C4vF2iN32S2W Xr/IZPG6bw2zxapdfxgt9l/xchDwWDNvDaNHS3MPm8e3r5NYPC739TJ5LPqe5bFz1l12jzvX 9rB5bF5S79G3ZRWjx/Eb25k8Pm+SC+CO4rJJSc3JLEst0rdL4MpYsXo9a8Fu3oq+L9kNjL3c XYwcHBICJhItf9y7GDmBTDGJC/fWs3UxcnEICSxllPjWcIMZwuljkvjUtIMRpIpNwFCi620X G4gtIpAt8ePbZBaQImaBVcwSUw6sYwVJCAv4SLzYPgesgUVAVWLnzNNgNq+Au0TLxtnMEOvk JP6/XMEEYnMKeEhMbpkJZgsB1az6sJdxAiPvAkaGVYyiqaXJBcVJ6blGesWJucWleel6yfm5 mxghIf51B+PSY1aHGAU4GJV4eCcU+4YIsSaWFVfmHmKU4GBWEuF1/AkU4k1JrKxKLcqPLyrN SS0+xMjEwSnVwCiYNkFV+f23YwdDpwl7S+rel7Fwlr1SmTfp3C/3Fvndsmtbzl+wkKjIqWXv YlQ64WCdtkd4z1dltf5t97Z/nvP/waN5Pd43+j1zjZ3WOusdD3KdeTBa6NCXwgy5HYH8b16v lkq8kXsge93tLs8nEWzOv/3ersyXDOVJ9Vlt+qA9e11SbvPTOUosxRmJhlrMRcWJAIxYbANP AgAA Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: m.szyprowski@samsung.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.49 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Tomasz Figa This patch adds device tree nodes for L2 cache controller present on Exynos4 SoCs. Signed-off-by: Tomasz Figa Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos4210.dtsi | 9 +++++++++ arch/arm/boot/dts/exynos4x12.dtsi | 14 ++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 536a747a8632..8b97f10f0926 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -64,6 +64,15 @@ reg = <0x10023CA0 0x20>; }; + l2c: l2-cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <2 2 1>; + }; + gic: interrupt-controller@10490000 { cpu-offset = <0x8000>; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 50b3c3f51e90..3e806d63e8bb 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -54,6 +54,20 @@ reg = <0x10023CA0 0x20>; }; + l2c: l2-cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <3 2 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <1>; + arm,prefetch-offset = <7>; + }; + clock: clock-controller@10030000 { compatible = "samsung,exynos4412-clock"; reg = <0x10030000 0x20000>;