From patchwork Fri Jan 23 14:22:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 43640 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f198.google.com (mail-lb0-f198.google.com [209.85.217.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 98287218DB for ; Fri, 23 Jan 2015 14:22:58 +0000 (UTC) Received: by mail-lb0-f198.google.com with SMTP id l4sf4414009lbv.1 for ; Fri, 23 Jan 2015 06:22:57 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=5pF/84xtJYSHlPTB6C3Rm6v06ZuSxsHdx2arrqDyn4I=; b=gfJPjJv16DCA9FU5mwa5rU68rJiGvv/Fa+zlcfPWNEiWI5Asr/y8GYvL59omylWnl/ vrZkg0ZhbeMFHP6W3csJwet1AZzTu1knZlyD4PbGss8thk0HU0xAT/2vubmkfV0M2uV5 JWPVq+my78SFmdcNYq+WDqfWk7wt0X4JzJ9SZxR1lKyxmDZI2JxOb/Ix8xuVCwxGX70Y mE3CVrRKkhOTmU+8LS4aPRKKmJUMqdfwsOALKvZYuPCHCrSUcrfHkCdCY7Oo/neCMtRb tG7/apbQhOTDYrTU6alfPq64UvX2X9Bqhx2PgjVymL/nIXoZ1iUErG4nNklZGQwxnYaz GJ7g== X-Gm-Message-State: ALoCoQknciZnez3bDufKOO0rlB7lmOcST6XWHqoVhi4vFcX6h+LbJRwZag6bhmMkB+tvX8d/LJLU X-Received: by 10.180.74.140 with SMTP id t12mr327287wiv.2.1422022977517; Fri, 23 Jan 2015 06:22:57 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.20.132 with SMTP id n4ls194420lae.6.gmail; Fri, 23 Jan 2015 06:22:57 -0800 (PST) X-Received: by 10.152.183.196 with SMTP id eo4mr7734848lac.0.1422022977343; Fri, 23 Jan 2015 06:22:57 -0800 (PST) Received: from mail-lb0-f176.google.com (mail-lb0-f176.google.com. [209.85.217.176]) by mx.google.com with ESMTPS id al1si1522141lbc.23.2015.01.23.06.22.57 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Jan 2015 06:22:57 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.176 as permitted sender) client-ip=209.85.217.176; Received: by mail-lb0-f176.google.com with SMTP id z12so7262785lbi.7 for ; Fri, 23 Jan 2015 06:22:57 -0800 (PST) X-Received: by 10.112.180.135 with SMTP id do7mr7476994lbc.23.1422022977168; Fri, 23 Jan 2015 06:22:57 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.112.9.200 with SMTP id c8csp270416lbb; Fri, 23 Jan 2015 06:22:56 -0800 (PST) X-Received: by 10.194.85.17 with SMTP id d17mr14127704wjz.61.1422022976377; Fri, 23 Jan 2015 06:22:56 -0800 (PST) Received: from mail-wg0-f45.google.com (mail-wg0-f45.google.com. [74.125.82.45]) by mx.google.com with ESMTPS id el10si2791075wid.58.2015.01.23.06.22.56 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Jan 2015 06:22:56 -0800 (PST) Received-SPF: pass (google.com: domain of daniel.thompson@linaro.org designates 74.125.82.45 as permitted sender) client-ip=74.125.82.45; Received: by mail-wg0-f45.google.com with SMTP id x12so7769086wgg.4 for ; Fri, 23 Jan 2015 06:22:56 -0800 (PST) X-Received: by 10.180.73.239 with SMTP id o15mr4271114wiv.14.1422022976073; Fri, 23 Jan 2015 06:22:56 -0800 (PST) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id bj3sm2058188wib.3.2015.01.23.06.22.54 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Jan 2015 06:22:55 -0800 (PST) From: Daniel Thompson To: Thomas Gleixner Cc: Daniel Thompson , Jason Cooper , Russell King , Will Deacon , Catalin Marinas , Marc Zyngier , Stephen Boyd , John Stultz , Steven Rostedt , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patches@linaro.org, linaro-kernel@lists.linaro.org, Sumit Semwal , Dirk Behme , Daniel Drake , Dmitry Pervushin , Tim Sander Subject: [PATCH 3.19-rc2 v15 2/8] irqchip: gic: Make gic_raise_softirq FIQ-safe Date: Fri, 23 Jan 2015 14:22:26 +0000 Message-Id: <1422022952-31552-3-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1422022952-31552-1-git-send-email-daniel.thompson@linaro.org> References: <1422022952-31552-1-git-send-email-daniel.thompson@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.thompson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , It is currently possible for FIQ handlers to re-enter gic_raise_softirq() and lock up. gic_raise_softirq() lock(x); -~-> FIQ handle_fiq() gic_raise_softirq() lock(x); <-- Lockup arch/arm/ uses IPIs to implement arch_irq_work_raise(), thus this issue renders it difficult for FIQ handlers to safely defer work to less restrictive calling contexts. This patch fixes the problem by converting the cpu_map_migration_lock into a rwlock making it safe to re-enter the function. Note that having made it safe to re-enter gic_raise_softirq() we no longer need to mask interrupts during gic_raise_softirq() because the b.L migration is always performed from task context. Signed-off-by: Daniel Thompson Cc: Thomas Gleixner Cc: Jason Cooper Cc: Russell King Cc: Marc Zyngier --- drivers/irqchip/irq-gic.c | 38 +++++++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index a9ed64dcc84b..c172176499f6 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -75,22 +75,25 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock); /* * This lock is used by the big.LITTLE migration code to ensure no IPIs * can be pended on the old core after the map has been updated. + * + * This lock may be locked for reading from both IRQ and FIQ handlers + * and therefore must not be locked for writing when these are enabled. */ #ifdef CONFIG_BL_SWITCHER -static DEFINE_RAW_SPINLOCK(cpu_map_migration_lock); +static DEFINE_RWLOCK(cpu_map_migration_lock); -static inline void bl_migration_lock(unsigned long *flags) +static inline void bl_migration_lock(void) { - raw_spin_lock_irqsave(&cpu_map_migration_lock, *flags); + read_lock(&cpu_map_migration_lock); } -static inline void bl_migration_unlock(unsigned long flags) +static inline void bl_migration_unlock(void) { - raw_spin_unlock_irqrestore(&cpu_map_migration_lock, flags); + read_unlock(&cpu_map_migration_lock); } #else -static inline void bl_migration_lock(unsigned long *flags) {} -static inline void bl_migration_unlock(unsigned long flags) {} +static inline void bl_migration_lock(void) {} +static inline void bl_migration_unlock(void) {} #endif /* @@ -640,12 +643,20 @@ static void __init gic_pm_init(struct gic_chip_data *gic) #endif #ifdef CONFIG_SMP +/* + * Raise the specified IPI on all cpus set in mask. + * + * This function is safe to call from all calling contexts, including + * FIQ handlers. It relies on bl_migration_lock() being multiply acquirable + * to avoid deadlocks when the function is re-entered at different + * exception levels. + */ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) { int cpu; - unsigned long flags, map = 0; + unsigned long map = 0; - bl_migration_lock(&flags); + bl_migration_lock(); /* Convert our logical CPU mask into a physical one. */ for_each_cpu(cpu, mask) @@ -660,7 +671,7 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) /* this always happens on GIC0 */ writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); - bl_migration_unlock(flags); + bl_migration_unlock(); } #endif @@ -708,7 +719,8 @@ int gic_get_cpu_id(unsigned int cpu) * Migrate all peripheral interrupts with a target matching the current CPU * to the interface corresponding to @new_cpu_id. The CPU interface mapping * is also updated. Targets to other CPU interfaces are unchanged. - * This must be called with IRQs locally disabled. + * This must be called from a task context and with IRQ and FIQ locally + * disabled. */ void gic_migrate_target(unsigned int new_cpu_id) { @@ -739,9 +751,9 @@ void gic_migrate_target(unsigned int new_cpu_id) * pending on the old cpu static. That means we can defer the * migration until after we have released the irq_controller_lock. */ - raw_spin_lock(&cpu_map_migration_lock); + write_lock(&cpu_map_migration_lock); gic_cpu_map[cpu] = 1 << new_cpu_id; - raw_spin_unlock(&cpu_map_migration_lock); + write_unlock(&cpu_map_migration_lock); /* * Find all the peripheral interrupts targetting the current