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[209.132.180.67]) by mx.google.com with ESMTP id h10si644608igy.78.2015.09.11.01.21.17; Fri, 11 Sep 2015 01:21:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751301AbbIKIVP (ORCPT + 7 others); Fri, 11 Sep 2015 04:21:15 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:6038 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751273AbbIKIVL (ORCPT ); Fri, 11 Sep 2015 04:21:11 -0400 Received: from 172.24.1.51 (EHLO SZXEML423-HUB.china.huawei.com) ([172.24.1.51]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BMS19884; Fri, 11 Sep 2015 16:18:51 +0800 (CST) Received: from u105-115.huawei.com (10.141.105.115) by SZXEML423-HUB.china.huawei.com (10.82.67.154) with Microsoft SMTP Server id 14.3.235.1; Fri, 11 Sep 2015 16:18:41 +0800 From: Chen Feng To: , , , , , , , CC: , , , , , Subject: [PATCH V2 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC Date: Fri, 11 Sep 2015 16:18:38 +0800 Message-ID: <1441959518-178696-3-git-send-email-puck.chen@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441959518-178696-1-git-send-email-puck.chen@hisilicon.com> References: <1441959518-178696-1-git-send-email-puck.chen@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.141.105.115] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0203.55F28E73.0282, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: e10255daa2b2532d89467f21be4ddcd9 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: puck.chen@hisilicon.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add reset driver for hi6220-hikey board,this driver supply deassert of IP. on hi6220 SoC. Signed-off-by: Chen Feng --- drivers/reset/Kconfig | 1 + drivers/reset/Makefile | 1 + drivers/reset/hisilicon/Kconfig | 5 ++ drivers/reset/hisilicon/Makefile | 1 + drivers/reset/hisilicon/hi6220_reset.c | 118 +++++++++++++++++++++++++++++++++ 5 files changed, 126 insertions(+) create mode 100644 drivers/reset/hisilicon/Kconfig create mode 100644 drivers/reset/hisilicon/Makefile create mode 100644 drivers/reset/hisilicon/hi6220_reset.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 0615f50..df37212 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER If unsure, say no. source "drivers/reset/sti/Kconfig" +source "drivers/reset/hisilicon/Kconfig" diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 157d421..331d7b2 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o obj-$(CONFIG_ARCH_STI) += sti/ +obj-$(CONFIG_ARCH_HISI) += hisilicon/ diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig new file mode 100644 index 0000000..26bf95a --- /dev/null +++ b/drivers/reset/hisilicon/Kconfig @@ -0,0 +1,5 @@ +config COMMON_RESET_HI6220 + tristate "Hi6220 Reset Driver" + depends on (ARCH_HISI && RESET_CONTROLLER) + help + Build the Hisilicon Hi6220 reset driver. diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile new file mode 100644 index 0000000..c932f86 --- /dev/null +++ b/drivers/reset/hisilicon/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c new file mode 100644 index 0000000..097133d --- /dev/null +++ b/drivers/reset/hisilicon/hi6220_reset.c @@ -0,0 +1,118 @@ +/* + * Hisilicon Hi6220 reset controller driver + * + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Feng Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ASSET_OFFSET 0x300 +#define DEASSET_OFFSET 0x304 + +struct hi6220_reset_data { + spinlock_t reset_lock; /*device spin-lock*/ + void __iomem *src_base; + void __iomem *asset_base; + void __iomem *deasset_base; + struct reset_controller_dev rc_dev; +}; + +static int hi6220_reset_assert(struct reset_controller_dev *rc_dev, + unsigned long idx) +{ + struct hi6220_reset_data *data = container_of(rc_dev, + struct hi6220_reset_data, + rc_dev); + + unsigned long flags; + int bank = idx >> 8; + int offset = idx & 0xff; + + spin_lock_irqsave(&data->reset_lock, flags); + + writel(BIT(offset), data->asset_base + (bank * 0x10)); + + spin_unlock_irqrestore(&data->reset_lock, flags); + + return 0; +} + +static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev, + unsigned long idx) +{ + struct hi6220_reset_data *data = container_of(rc_dev, + struct hi6220_reset_data, + rc_dev); + + unsigned long flags; + int bank = idx >> 8; + int offset = idx & 0xff; + + spin_lock_irqsave(&data->reset_lock, flags); + + writel(BIT(offset), data->deasset_base + (bank * 0x10)); + + spin_unlock_irqrestore(&data->reset_lock, flags); + + return 0; +} + +static struct reset_control_ops hi6220_reset_ops = { + .assert = hi6220_reset_assert, + .deassert = hi6220_reset_deassert, +}; + +static int __init hi6220_reset_init(void) +{ + int ret; + struct device_node *np; + struct hi6220_reset_data *data; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220_reset_ctl"); + if (!np) { + ret = -ENXIO; + goto err_alloc; + } + spin_lock_init(&data->reset_lock); + data->src_base = of_iomap(np, 0); + if (!data->src_base) { + ret = -ENOMEM; + goto err_alloc; + } + + data->asset_base = data->src_base + ASSET_OFFSET; + data->deasset_base = data->src_base + DEASSET_OFFSET; + data->rc_dev.owner = THIS_MODULE; + data->rc_dev.nr_resets = SZ_4K; + data->rc_dev.ops = &hi6220_reset_ops; + data->rc_dev.of_node = np; + + if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) + reset_controller_register(&data->rc_dev); + + return 0; + +err_alloc: + kfree(data); + return ret; +} + +postcore_initcall(hi6220_reset_init);