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[209.132.180.67]) by mx.google.com with ESMTP id xl6si28351607pbc.74.2015.09.14.20.59.22; Mon, 14 Sep 2015 20:59:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752240AbbIOD6r (ORCPT + 7 others); Mon, 14 Sep 2015 23:58:47 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:44360 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751981AbbIOD6q (ORCPT ); Mon, 14 Sep 2015 23:58:46 -0400 Received: from 172.24.1.47 (EHLO SZXEML423-HUB.china.huawei.com) ([172.24.1.47]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BMW80173; Tue, 15 Sep 2015 11:58:37 +0800 (CST) Received: from u105-115.huawei.com (10.141.105.115) by SZXEML423-HUB.china.huawei.com (10.82.67.154) with Microsoft SMTP Server id 14.3.235.1; Tue, 15 Sep 2015 11:58:26 +0800 From: Chen Feng To: , , , , , , , , CC: , , , , , Subject: [PATCH V3 2/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Date: Tue, 15 Sep 2015 11:58:23 +0800 Message-ID: <1442289504-183550-2-git-send-email-puck.chen@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442289504-183550-1-git-send-email-puck.chen@hisilicon.com> References: <1442289504-183550-1-git-send-email-puck.chen@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.141.105.115] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A150209.55F79770.0032, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 101b3af8dda5a6db3ee98f9ba37d92ea Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: puck.chen@hisilicon.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add DT bindings documentation for hi6220 SoC reset controller. Signed-off-by: Chen Feng --- .../bindings/reset/hisilicon,hi6220-reset.txt | 97 ++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt new file mode 100644 index 0000000..200dc8e --- /dev/null +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt @@ -0,0 +1,97 @@ +Hisilicon System Reset Controller +====================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +The reset controller node must be a sub-node of the chip controller +node on SoCs. + +Required properties: +- compatible: may be "hisilicon,hi6220_reset_ctl" +- reg: should be register base and length as documented in the + datasheet +- #reset-cells: 1, see below + +Example: + + reset_ctrl: reset_ctrl@f7030000 { + compatible = "hisilicon,hi6220_reset_ctl"; + reg = <0x0 0xf7030000 0x0 0x1000>; + #reset-cells = <1>; + }; + +Specifying reset lines connected to IP modules +============================================== +example: + + uart1: uart1@..... { + ... + resets = <&reset_ctrl 0x305>; + ... + }; + +The following RESET_INDEX values are valid for hi6220 SoC: + PERIPH_RSTDIS0_MMC0 = 0x000, + PERIPH_RSTDIS0_MMC1 = 0x001, + PERIPH_RSTDIS0_MMC2 = 0x002, + PERIPH_RSTDIS0_NANDC = 0x003, + PERIPH_RSTDIS0_USBOTG_BUS = 0x004, + PERIPH_RSTDIS0_POR_PICOPHY = 0x005, + PERIPH_RSTDIS0_USBOTG = 0x006, + PERIPH_RSTDIS0_USBOTG_32K = 0x007, + + PERIPH_RSTDIS1_HIFI = 0x100, + PERIPH_RSTDIS1_DIGACODEC = 0x105, + + PERIPH_RSTEN2_IPF = 0x200, + PERIPH_RSTEN2_SOCP = 0x201, + PERIPH_RSTEN2_DMAC = 0x202, + PERIPH_RSTEN2_SECENG = 0x203, + PERIPH_RSTEN2_ABB = 0x204, + PERIPH_RSTEN2_HPM0 = 0x205, + PERIPH_RSTEN2_HPM1 = 0x206, + PERIPH_RSTEN2_HPM2 = 0x207, + PERIPH_RSTEN2_HPM3 = 0x208, + + PERIPH_RSTEN3_CSSYS = 0x300, + PERIPH_RSTEN3_I2C0 = 0x301, + PERIPH_RSTEN3_I2C1 = 0x302, + PERIPH_RSTEN3_I2C2 = 0x303, + PERIPH_RSTEN3_I2C3 = 0x304, + PERIPH_RSTEN3_UART1 = 0x305, + PERIPH_RSTEN3_UART2 = 0x306, + PERIPH_RSTEN3_UART3 = 0x307, + PERIPH_RSTEN3_UART4 = 0x308, + PERIPH_RSTEN3_SSP = 0x309, + PERIPH_RSTEN3_PWM = 0x30a, + PERIPH_RSTEN3_BLPWM = 0x30b, + PERIPH_RSTEN3_TSENSOR = 0x30c, + PERIPH_RSTEN3_DAPB = 0x312, + PERIPH_RSTEN3_HKADC = 0x313, + PERIPH_RSTEN3_CODEC_SSI = 0x314, + PERIPH_RSTEN3_PMUSSI1 = 0x316, + + PERIPH_RSTEN8_RS0 = 0x400, + PERIPH_RSTEN8_RS2 = 0x401, + PERIPH_RSTEN8_RS3 = 0x402, + PERIPH_RSTEN8_MS0 = 0x403, + PERIPH_RSTEN8_MS2 = 0x405, + PERIPH_RSTEN8_XG2RAM0 = 0x406, + PERIPH_RSTEN8_X2SRAM_TZMA = 0x407, + PERIPH_RSTEN8_SRAM = 0x408, + PERIPH_RSTEN8_HARQ = 0x40a, + PERIPH_RSTEN8_DDRC = 0x40c, + PERIPH_RSTEN8_DDRC_APB = 0x40d, + PERIPH_RSTEN8_DDRPACK_APB = 0x40e, + PERIPH_RSTEN8_DDRT = 0x411, + + PERIPH_RSDIST9_CARM_DAP = 0x500, + PERIPH_RSDIST9_CARM_ATB = 0x501, + PERIPH_RSDIST9_CARM_LBUS = 0x502, + PERIPH_RSDIST9_CARM_POR = 0x503, + PERIPH_RSDIST9_CARM_CORE = 0x504, + PERIPH_RSDIST9_CARM_DBG = 0x505, + PERIPH_RSDIST9_CARM_L2 = 0x506, + PERIPH_RSDIST9_CARM_SOCDBG = 0x507, + PERIPH_RSDIST9_CARM_ETM = 0x508,