From patchwork Tue Dec 8 13:46:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 57873 Delivered-To: patch@linaro.org Received: by 10.112.147.194 with SMTP id tm2csp36769lbb; Tue, 8 Dec 2015 05:47:20 -0800 (PST) X-Received: by 10.98.71.6 with SMTP id u6mr4965940pfa.122.1449582439107; Tue, 08 Dec 2015 05:47:19 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id cm4si5438298pad.81.2015.12.08.05.47.18; Tue, 08 Dec 2015 05:47:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756606AbbLHNrR (ORCPT + 28 others); Tue, 8 Dec 2015 08:47:17 -0500 Received: from mailout3.w1.samsung.com ([210.118.77.13]:13686 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756355AbbLHNrO (ORCPT ); Tue, 8 Dec 2015 08:47:14 -0500 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZ100LSOKYNXQA0@mailout3.w1.samsung.com>; Tue, 08 Dec 2015 13:47:11 +0000 (GMT) X-AuditID: cbfec7f5-f79b16d000005389-ba-5666df5f84ed Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 7B.3F.21385.F5FD6665; Tue, 8 Dec 2015 13:47:11 +0000 (GMT) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZ1001MIKYJFT20@eusync4.samsung.com>; Tue, 08 Dec 2015 13:47:11 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Tomasz Figa , Mike Turquette , Krzysztof Kozlowski , Kukjin Kim Subject: [PATCH 2/2] ARM: dts: exynos542x: add GSCL block parent clock management to pm domain Date: Tue, 08 Dec 2015 14:46:55 +0100 Message-id: <1449582415-30164-2-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 In-reply-to: <1449582415-30164-1-git-send-email-m.szyprowski@samsung.com> References: <1449582415-30164-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOLMWRmVeSWpSXmKPExsVy+t/xa7rx99PCDOZ2KVu8fmFo0f/4NbPF 5V1z2CxmnN/HZLH2yF12i4unXC0Ov2lntVi16w+jA4fH+xut7B47Z91l99i0qpPNo2/LKkaP z5vkAlijuGxSUnMyy1KL9O0SuDKWnnvKXrCdvWJh2032Bsa5bF2MnBwSAiYSC+/sZYKwxSQu 3FsPFOfiEBJYyijxc9I5JginiUli1sclYB1sAoYSXW+7wGwRAWeJhqmNYN3MAv8ZJRa9dgSx hQUSJFZd+wQWZxFQlVjcdA3M5hXwkPh5+hcrxDY5if8vV4DFOQU8JdY1TWUEsYWAapbPP8g6 gZF3ASPDKkbR1NLkguKk9FwjveLE3OLSvHS95PzcTYyQ4Pq6g3HpMatDjAIcjEo8vAonU8OE WBPLiitzDzFKcDArifD+uJsWJsSbklhZlVqUH19UmpNafIhRmoNFSZx35q73IUIC6Yklqdmp qQWpRTBZJg5OqQbGpuVq5+euX2o/4fSe0tUrXFWmtL1OZXvL5z/99wru/d6R858svKhzLX/L hN0fJn6VYJqYHrrand26ROWHYO9Oo3/er2/cD18YeDsrTYundf+8Q4W/8i6sivdneXyMXe1d BauXpnbV290/2h/vXXAs1zhcOTVhq8GLD8xLVZfx2txuN3Z4vCpOVImlOCPRUIu5qDgRAM2c r+kqAgAA Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for restoring GScaler parent clocks configuration when GSCL power domain is turned on. Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos5420.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 1.9.2 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 48a0a55..912143e 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -252,8 +252,10 @@ compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; #power-domain-cells = <0>; - clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; - clock-names = "asb0", "asb1"; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK300_GSCL>, + <&clock CLK_MOUT_USER_ACLK300_GSCL>, <&clock CLK_GSCL0>, + <&clock CLK_GSCL1>; + clock-names = "oscclk", "pclk0", "clk0", "asb0", "asb1"; }; isp_pd: power-domain@10044020 {