From patchwork Fri Dec 18 09:44:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 58634 Delivered-To: patch@linaro.org Received: by 10.112.89.199 with SMTP id bq7csp904724lbb; Fri, 18 Dec 2015 01:45:11 -0800 (PST) X-Received: by 10.66.120.200 with SMTP id le8mr3736830pab.61.1450431911460; Fri, 18 Dec 2015 01:45:11 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ad8si22921385pad.214.2015.12.18.01.45.11; Fri, 18 Dec 2015 01:45:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=neutral (body hash did not verify) header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752414AbbLRJpI (ORCPT + 29 others); Fri, 18 Dec 2015 04:45:08 -0500 Received: from mail-lf0-f50.google.com ([209.85.215.50]:36618 "EHLO mail-lf0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751388AbbLRJpD (ORCPT ); Fri, 18 Dec 2015 04:45:03 -0500 Received: by mail-lf0-f50.google.com with SMTP id z124so64162161lfa.3 for ; Fri, 18 Dec 2015 01:45:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=63Lo+y7cpDOW10lf9c4l5Ac+RrF06rZ+cL/Yb/f0G38=; b=FB8Sq/XXTbg9nmFJ43rAjaba+vObp3DBfL2lp6Z85mv7E3HkOQUnBkBh0kptp4CaEJ 3z9NsV0UXNYw5Hu71j/XowLC7aWeo/A8B7Z0kZ8J+tPKmGPOIjkJFjGQXTOtsvWyXYjj xdzE1gQejLFdQUiFZ3rlVmBZ5NIRAZmb1v3Nk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=63Lo+y7cpDOW10lf9c4l5Ac+RrF06rZ+cL/Yb/f0G38=; b=IpyX/WFm23Da3NlmB2/13YV8IuZvotzYJOsX/wLo9rms/UlCpNemc9Ln9wwAaxeijK tCZ+8rEBiSkKduvt6aGcUlkYuFw3YBJJdZhJ/wJ3E3h4gQkx1R7XLwjUqTG1pLsvMq0K SX2qRoz/1JMDCMHucjvRpXkhBzLI6fGjhfvplFdog/4z2Zx+dRV+uQyt0bnpTHTJoFrM ETgXJxpADraGqj79sRZ8w/XTgo/13D96P5G1SdqPNRffcXDmPVP950a1dauIS6m7lbR9 6O3a2b+H3AExSnRdpawdgzbEg+Y6VXRe75we4cQ4T0aXgb0rihy+LKLqx5YCUP86CX1w KJoA== X-Gm-Message-State: ALoCoQnroUwx9lCiAsVWCbarKe6Z92aXRPD7XDYX/0psFOMWpnSfemvrn++hTCDCTw5MU4nGQxanYZeGjbSAF/SHrEmiKBoUrw== X-Received: by 10.25.165.17 with SMTP id o17mr941224lfe.145.1450431901063; Fri, 18 Dec 2015 01:45:01 -0800 (PST) Received: from localhost.localdomain ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id e2sm2625076lfb.25.2015.12.18.01.44.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Dec 2015 01:45:00 -0800 (PST) From: Linus Walleij To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Arnd Bergmann Cc: linux-kernel@vger.kernel.org, Linus Walleij Subject: [PATCH] irqchip: gic: Kconfig the number of instances Date: Fri, 18 Dec 2015 10:44:53 +0100 Message-Id: <1450431893-7867-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is currently a hack in the GIC driver making it possible to pass the number of GIC instances from the platform-specific include files and thus override the variable MAX_GIC_NR. With multiplatform deployments, this will not work as we need to get rid of the platform-specific include files. It turns out that this feature is only used by the RealView platform which has a cascaded GIC. So move the configuration to Kconfig and bump to 2 instances if we're building for the RealView. The include file hacks can then be removed. Tested on the ARM PB11MPCore with its cascaded GIC. Suggested-by: Arnd Bergmann Signed-off-by: Linus Walleij --- drivers/irqchip/Kconfig | 5 +++++ drivers/irqchip/irq-gic.c | 24 ++++++++++-------------- 2 files changed, 15 insertions(+), 14 deletions(-) -- 2.4.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 4d7294e5d982..bf29a8b2b7c5 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -8,6 +8,11 @@ config ARM_GIC select IRQ_DOMAIN_HIERARCHY select MULTI_IRQ_HANDLER +config ARM_GIC_MAX_NR + int + default 2 if ARCH_REALVIEW + default 1 + config ARM_GIC_V2M bool depends on ARM_GIC diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index abf2ffaed392..006a83838857 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -99,11 +99,7 @@ static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; -#ifndef MAX_GIC_NR -#define MAX_GIC_NR 1 -#endif - -static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; +static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; #ifdef CONFIG_GIC_NON_BANKED static void __iomem *gic_get_percpu_base(union gic_base *base) @@ -417,7 +413,7 @@ static struct irq_chip gic_eoimode1_chip = { void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) { - if (gic_nr >= MAX_GIC_NR) + if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) BUG(); irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, &gic_data[gic_nr]); @@ -524,7 +520,7 @@ int gic_cpu_if_down(unsigned int gic_nr) void __iomem *cpu_base; u32 val = 0; - if (gic_nr >= MAX_GIC_NR) + if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) return -EINVAL; cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); @@ -548,7 +544,7 @@ static void gic_dist_save(unsigned int gic_nr) void __iomem *dist_base; int i; - if (gic_nr >= MAX_GIC_NR) + if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) BUG(); gic_irqs = gic_data[gic_nr].gic_irqs; @@ -587,7 +583,7 @@ static void gic_dist_restore(unsigned int gic_nr) unsigned int i; void __iomem *dist_base; - if (gic_nr >= MAX_GIC_NR) + if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) BUG(); gic_irqs = gic_data[gic_nr].gic_irqs; @@ -634,7 +630,7 @@ static void gic_cpu_save(unsigned int gic_nr) void __iomem *dist_base; void __iomem *cpu_base; - if (gic_nr >= MAX_GIC_NR) + if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) BUG(); dist_base = gic_data_dist_base(&gic_data[gic_nr]); @@ -664,7 +660,7 @@ static void gic_cpu_restore(unsigned int gic_nr) void __iomem *dist_base; void __iomem *cpu_base; - if (gic_nr >= MAX_GIC_NR) + if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) BUG(); dist_base = gic_data_dist_base(&gic_data[gic_nr]); @@ -703,7 +699,7 @@ static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) { int i; - for (i = 0; i < MAX_GIC_NR; i++) { + for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { #ifdef CONFIG_GIC_NON_BANKED /* Skip over unused GICs */ if (!gic_data[i].get_base) @@ -835,7 +831,7 @@ void gic_migrate_target(unsigned int new_cpu_id) int i, ror_val, cpu = smp_processor_id(); u32 val, cur_target_mask, active_mask; - if (gic_nr >= MAX_GIC_NR) + if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) BUG(); dist_base = gic_data_dist_base(&gic_data[gic_nr]); @@ -1040,7 +1036,7 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, struct gic_chip_data *gic; int gic_irqs, irq_base, i; - BUG_ON(gic_nr >= MAX_GIC_NR); + BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); gic_check_cpu_features();