From patchwork Sun Dec 20 20:52:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 58772 Delivered-To: patches@linaro.org Received: by 10.112.89.199 with SMTP id bq7csp2228060lbb; Sun, 20 Dec 2015 12:53:07 -0800 (PST) X-Received: by 10.194.134.134 with SMTP id pk6mr19478310wjb.21.1450644787863; Sun, 20 Dec 2015 12:53:07 -0800 (PST) Return-Path: Received: from mail-wm0-x22f.google.com (mail-wm0-x22f.google.com. [2a00:1450:400c:c09::22f]) by mx.google.com with ESMTPS id vu8si44160825wjc.28.2015.12.20.12.53.07 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 20 Dec 2015 12:53:07 -0800 (PST) Received-SPF: pass (google.com: domain of daniel.thompson@linaro.org designates 2a00:1450:400c:c09::22f as permitted sender) client-ip=2a00:1450:400c:c09::22f; Authentication-Results: mx.google.com; spf=pass (google.com: domain of daniel.thompson@linaro.org designates 2a00:1450:400c:c09::22f as permitted sender) smtp.mailfrom=daniel.thompson@linaro.org; dkim=pass header.i=@linaro.org Received: by mail-wm0-x22f.google.com with SMTP id l126so45800509wml.1 for ; Sun, 20 Dec 2015 12:53:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IWZSPN0rP9tdy/RCzOJnuSLWbjF7LxUnMLSXXarc+H8=; b=O7w2pycBZs2365EmkWPLVDg147BIhDSBDUEOXTCd/a892FDcnFO3ErLPr/F+NyqPQo n1OFYgpUjvoRmY8AQfVx2MJZSMo8nFTQ9tibd9axU+5bQQQE1T3KYB7iG1ETFF+eKcwJ EVPITbgIMUbcGvywoV4nwghwHkn8AgaAqVPTo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IWZSPN0rP9tdy/RCzOJnuSLWbjF7LxUnMLSXXarc+H8=; b=VHmgpnjF8nzJdkIjOV+l9/iKhg4V2WjykNfOJNqgSgHDxRSMG6lTkg5twSd7PdERyB wkzlfpiLJupILMp3sCarmLU2sU2WoV8aefbGxuLXLGKIU/wFC50afGTkP5nhIC4TeMn2 xkYS3/MXihQmxMVCX4cJPoSJRT5dcnmDE2o30mrbsJK0xzU+exvflPlj9TBbbgjU1v8g 0Hw/zX73PYnalR1ns+wvpOFz2sK/0FnFTL6UA3jiZmjRIMhqpG37LptC7e8kyzUY4b7O nmNrgRCHGLqj0zToL7m4qUkBgFkT87tdUbQM04sBzRr1SuFUgoTfB7ZKIrw/02aO7Ns2 hmKw== X-Gm-Message-State: ALoCoQlcFTKG3FmXdTRu2twvQyN3RaBGUUNNARufEijrXP4p21cDBGA9tuH+EZIkQFkVx/ACU63oSAx5SOE5alcg8fGl1+6xQQ== X-Received: by 10.194.117.163 with SMTP id kf3mr16701914wjb.139.1450644787617; Sun, 20 Dec 2015 12:53:07 -0800 (PST) Return-Path: Received: from wychelm.lan (cpc4-aztw19-0-0-cust71.18-1.cable.virginm.net. [82.33.25.72]) by smtp.gmail.com with ESMTPSA id i84sm16913134wmc.20.2015.12.20.12.53.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 20 Dec 2015 12:53:06 -0800 (PST) From: Daniel Thompson To: Thomas Gleixner , Jason Cooper , Russell King , Marc Zyngier Cc: Daniel Thompson , Will Deacon , Catalin Marinas , Stephen Boyd , John Stultz , Steven Rostedt , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patches@linaro.org, linaro-kernel@lists.linaro.org, Sumit Semwal , Dirk Behme , Daniel Drake , Dmitry Pervushin , Tim Sander , Petr Mladek Subject: [PATCH 4.4-rc5 v22 4/4] ARM: Allow IPI_CPU_BACKTRACE to exploit FIQ Date: Sun, 20 Dec 2015 20:52:37 +0000 Message-Id: <1450644757-18734-5-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1450644757-18734-1-git-send-email-daniel.thompson@linaro.org> References: <1450644757-18734-1-git-send-email-daniel.thompson@linaro.org> The GIC (v1 & v2) driver allows its implementation of handle_arch_irq() to be called from the FIQ handler but currently the ARM code is not able to exploit this. Extend handle_fiq_as_nmi() to call handle_arch_irq(). This will affect all interrupt controllers, including ones that do not support FIQ. This is OK because a spurious FIQ is normally fatal. Handling a spurious FIQ like a normal interrupt does risk deadlock but does give us a chance of surviving long enough to get an error message out. We also extend the SMP code to indicate to irq drivers which IPIs they should seek to implement using FIQ. Signed-off-by: Daniel Thompson --- arch/arm/include/asm/smp.h | 9 +++++++++ arch/arm/kernel/smp.c | 6 ++++++ arch/arm/kernel/traps.c | 9 ++++++++- 3 files changed, 23 insertions(+), 1 deletion(-) -- 2.5.0 diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 3d6dc8b460e4..daf869cff02e 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -18,6 +18,15 @@ # error " included in non-SMP build" #endif +/* + * Identify which IPIs are safe for the irqchip to handle using FIQ. + * + * This information is advisory. The interrupt controller may not be capable + * of routing these IPIs to FIQ and the kernel will continue to work if they + * are routed to IRQ as normal. + */ +#define SMP_IPI_FIQ_MASK 0x80 + #define raw_smp_processor_id() (current_thread_info()->cpu) struct seq_file; diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index fe517f1e88d8..853089e1aa8a 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -639,6 +639,11 @@ void handle_IPI(int ipinr, struct pt_regs *regs) break; case IPI_CPU_BACKTRACE: + if (in_nmi()) { + nmi_cpu_backtrace(regs); + break; + } + irq_enter(); nmi_cpu_backtrace(regs); irq_exit(); @@ -750,6 +755,7 @@ static void raise_nmi(cpumask_t *mask) if (cpumask_test_cpu(smp_processor_id(), mask) && irqs_disabled()) nmi_cpu_backtrace(NULL); + BUILD_BUG_ON(SMP_IPI_FIQ_MASK != BIT(IPI_CPU_BACKTRACE)); smp_cross_call(mask, IPI_CPU_BACKTRACE); } diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index bc698383e822..a04426ee7684 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -479,7 +479,14 @@ asmlinkage void __exception_irq_entry handle_fiq_as_nmi(struct pt_regs *regs) nmi_enter(); - /* nop. FIQ handlers for special arch/arm features can be added here. */ + /* + * Either the interrupt controller supports FIQ, meaning it will + * do the right thing with this call, or we will end up treating a + * spurious FIQ (which is normally fatal) as though it were an IRQ + * which, although it risks deadlock, still gives us a sporting + * chance of surviving long enough to log errors. + */ + handle_arch_irq(regs); nmi_exit();