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[209.132.180.67]) by mx.google.com with ESMTP id 7si44761480pfk.172.2016.02.01.00.00.30; Mon, 01 Feb 2016 00:00:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751807AbcBAIAZ (ORCPT + 30 others); Mon, 1 Feb 2016 03:00:25 -0500 Received: from mail-pf0-f169.google.com ([209.85.192.169]:32869 "EHLO mail-pf0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751587AbcBAIAU (ORCPT ); Mon, 1 Feb 2016 03:00:20 -0500 Received: by mail-pf0-f169.google.com with SMTP id x125so79800075pfb.0 for ; Mon, 01 Feb 2016 00:00:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=Q3qq7ddYfdPF6Q5DINBlF/B7Z8oYwOxgJzpLphjbrwBXwLula0YyrqP6XcG3NmU191 TmkrWKwcFyXLnoqkW6ZsLP4aXRY53uKHEozpf/IKY9X32vLcU8t1XfAjKYZPUz2lnaKL WIsepJegLeC2rFB+5Qb6QAqyM3evJ8P1phNsY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=RG9echSAb3NI/Zr5gGVWCth9lDJNiFQwpuRgwABRRnDej9AWtSYMpymmZnC5dO/3O/ 3PUpdxJdS8vcXLBDIRzYZXKBmMJWVB/HK+E03Efhr51dktfF3p2Btinc9exGikvky87R QU6qc4EpP9YLWarDwYTkyOvwm/fjVKOqccY/94/2q2myic+jHSEEDAIcllLKYHEuKDfp uxW7AzSzgLigbi4xnchV+uaQ6ac372GwehiIpfW5ShSpNiw8i9RuiQrWMp3NgYEd10Ic uq9gI1woG+6zEG7Hbmi8x/CIs1Nn+LKDtIm12Uvf+WIls/VhNt6XEKE97n1pZuj816Xz qlUQ== X-Gm-Message-State: AG10YOTYEq1gHYDDB8bfF089bJnWP2JoE9atCnktF0R7AorQO/rtQTix1VKlAg03dPHGioFL X-Received: by 10.98.68.220 with SMTP id m89mr36006412pfi.65.1454313619535; Mon, 01 Feb 2016 00:00:19 -0800 (PST) Received: from zcy-ubuntu.spreadtrum.com ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id o4sm40799282pfa.85.2016.02.01.00.00.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Feb 2016 00:00:18 -0800 (PST) From: Chunyan Zhang To: mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com Cc: robh@kernel.org, broonie@kernel.org, pratikp@codeaurora.org, nicolas.guion@st.com, corbet@lwn.net, mark.rutland@arm.com, zhang.lyra@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-api@vger.kernel.orgi, linux-doc@vger.kernel.org Subject: [PATCH 5/6] coresight-stm: Bindings for System Trace Macrocell Date: Mon, 1 Feb 2016 15:58:48 +0800 Message-Id: <1454313529-8860-6-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454313529-8860-1-git-send-email-zhang.chunyan@linaro.org> References: <1454313529-8860-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mathieu Poirier The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier Acked-by: Rob Herring Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 62938eb..93147c0c 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -19,6 +19,7 @@ its hardware characteristcs. - "arm,coresight-etm3x", "arm,primecell"; - "arm,coresight-etm4x", "arm,primecell"; - "qcom,coresight-replicator1x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -36,6 +37,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -202,3 +211,22 @@ Example: }; }; }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name.