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[209.132.180.67]) by mx.google.com with ESMTP id r79si44805350pfb.75.2016.02.01.00.21.19; Mon, 01 Feb 2016 00:21:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752592AbcBAIVR (ORCPT + 30 others); Mon, 1 Feb 2016 03:21:17 -0500 Received: from mail-pa0-f47.google.com ([209.85.220.47]:33500 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751233AbcBAIVO (ORCPT ); Mon, 1 Feb 2016 03:21:14 -0500 Received: by mail-pa0-f47.google.com with SMTP id cy9so78173146pac.0 for ; Mon, 01 Feb 2016 00:21:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=a925O0pvofvk/LjzCfvJmN7P04A0LNqHOC0HrBKwnDJNfcwdbUDYYFfGih8fq71r39 WA25YFZAYnPYU+NszA5nSGSOWFkiIrNVuld/fzho79O1r1f8m6cev61BqKpaEA0TAYVb v/5R+cfkZD/4pLZGvYc64zgIGfcrNWkUL3Kqw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=jPXTMa5suZfkel+IQZt/F6b2F7J0RNvpBNmHZJ5rT2e9pPpZbxGMr1X1pbq3ihmTnV PsA0rvJsM3E9T3q5jAnQeZqjwMo2kvmmVcpC5eSHm0FwdAzS99Y7VD2Du3H5KtGbs9wT frc9r6wWbhy/07B4be9+8u/F/opn4+o8YeQ/GE2W95i3zvj66AUiPRUCOiVO73Sy/c2D oqKuXPtgMasOnb08RYkTMBrz0QOiOy70HKvVKyhWiv9V2N3IQ3BKAQpt5N/YmYiyVrHB zm/mFNmZMOpeQNzmI7YRDGH9GpyCauQhklBANOnGJVgKsrCuX1vx2E0c37y/Nsnpox4a 8OLg== X-Gm-Message-State: AG10YOTAthc+iBbFj7dofqZ00apLpJCUAVNHLOuk7eHhiQOTdN0CY2Ppdr0Ajl7siFigeRky X-Received: by 10.66.164.102 with SMTP id yp6mr36021348pab.25.1454314874255; Mon, 01 Feb 2016 00:21:14 -0800 (PST) Received: from zcy-ubuntu.spreadtrum.com ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id b63sm41053804pfj.25.2016.02.01.00.21.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Feb 2016 00:21:13 -0800 (PST) From: Chunyan Zhang To: mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com Cc: robh@kernel.org, broonie@kernel.org, pratikp@codeaurora.org, nicolas.guion@st.com, corbet@lwn.net, mark.rutland@arm.com, zhang.lyra@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-api@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH 5/6] coresight-stm: Bindings for System Trace Macrocell Date: Mon, 1 Feb 2016 16:20:57 +0800 Message-Id: <1454314857-9340-1-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454313529-8860-6-git-send-email-zhang.chunyan@linaro.org> References: <1454313529-8860-6-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mathieu Poirier The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier Acked-by: Rob Herring Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 62938eb..93147c0c 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -19,6 +19,7 @@ its hardware characteristcs. - "arm,coresight-etm3x", "arm,primecell"; - "arm,coresight-etm4x", "arm,primecell"; - "qcom,coresight-replicator1x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -36,6 +37,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -202,3 +211,22 @@ Example: }; }; }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name.