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[209.132.180.67]) by mx.google.com with ESMTP id xp4si7798711pab.1.2016.02.03.00.16.57; Wed, 03 Feb 2016 00:16:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756892AbcBCIQw (ORCPT + 30 others); Wed, 3 Feb 2016 03:16:52 -0500 Received: from mail-pf0-f177.google.com ([209.85.192.177]:36851 "EHLO mail-pf0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756862AbcBCIQs (ORCPT ); Wed, 3 Feb 2016 03:16:48 -0500 Received: by mail-pf0-f177.google.com with SMTP id n128so9814520pfn.3 for ; Wed, 03 Feb 2016 00:16:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=Y2rrewJi5+b9JVFYpZfDeaeVqi+LjKOriVGQ+DDbHrymkW1OA10JL5GWWTUJCgIGsi LrWmhLMHssiRGwrUocc77aWoJlhUj5U4MokTgHbRMEdR2Qm4lKtMo5CyI6vObeugjoJF BC8ikXfmhtpTiR4J9a58QresEl3zmRKYcGeXA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=aOmQbRIAM4bv8prz7DLy273277ywG+QIuovkLPiiGEBX+qvA7sC+Ql5YFrJl675msp Nr+Ps6q7HuSlbtC9A+MuYE1wzt7G5cJtOIvptnVtupBC+tTZuYMvU8nmvtaRNr0e+vqw yCkNFGuKxm9nRXz7gfs7u3Idl7RXRbLaRjjPVoTWndorJ3s9bElb8tskjuxs1ic49odV K2SO5afg13RFgn4HGLpwvy1sJ2f6ErhcYnmsq9tbX8GumWpGMyPpuo95lAHlZrpzC+sO VhjwHYufpl6rjr2PuouIZeV+S3KYUfNgJDVH6mASDhjsRV68/CsDwKRimjCJyXw1Y0Sv kKIg== X-Gm-Message-State: AG10YOTliw6Avx7AIpy+Ffc7d3Xn8Iu5i1Cu03UvvVwog8icA/cdS2N35rh3eOtjbOeWv5fE X-Received: by 10.98.72.215 with SMTP id q84mr310366pfi.152.1454487407364; Wed, 03 Feb 2016 00:16:47 -0800 (PST) Received: from zcy-ubuntu.spreadtrum.com ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id tp6sm7725820pab.25.2016.02.03.00.16.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 03 Feb 2016 00:16:46 -0800 (PST) From: Chunyan Zhang To: mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com Cc: robh@kernel.org, broonie@kernel.org, pratikp@codeaurora.org, nicolas.guion@st.com, corbet@lwn.net, mark.rutland@arm.com, mike.leach@arm.com, tor@ti.com, al.grant@arm.com, zhang.lyra@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-api@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH V2 5/6] coresight-stm: Bindings for System Trace Macrocell Date: Wed, 3 Feb 2016 16:15:36 +0800 Message-Id: <1454487337-30184-6-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454487337-30184-1-git-send-email-zhang.chunyan@linaro.org> References: <1454487337-30184-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mathieu Poirier The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier Acked-by: Rob Herring Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 62938eb..93147c0c 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -19,6 +19,7 @@ its hardware characteristcs. - "arm,coresight-etm3x", "arm,primecell"; - "arm,coresight-etm4x", "arm,primecell"; - "qcom,coresight-replicator1x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -36,6 +37,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -202,3 +211,22 @@ Example: }; }; }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name.