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[209.132.180.67]) by mx.google.com with ESMTP id i10si44604158pat.47.2016.02.29.10.55.55; Mon, 29 Feb 2016 10:55:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753978AbcB2Szh (ORCPT + 30 others); Mon, 29 Feb 2016 13:55:37 -0500 Received: from mail-pf0-f180.google.com ([209.85.192.180]:33422 "EHLO mail-pf0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753641AbcB2Syw (ORCPT ); Mon, 29 Feb 2016 13:54:52 -0500 Received: by mail-pf0-f180.google.com with SMTP id 124so35205953pfg.0 for ; Mon, 29 Feb 2016 10:54:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4Nwi6NQNTYcnRVBD3g/5058yNqzeG1RJWvkYxn8oDJk=; b=HIOr+HbZuFs69A4nL02iLQhiwUxgRwbqbXsiG0IF9eZUMxdejcvFE9RwFlZLY5dHEV XNmlKi2eY8o2WJIO1nfVw0MxGiC5v9UfYYSH3mKUJWSANNp0EcAGkVw/kloM+BTstqT1 lRNeo7SgzhGFbuKcAIUOYSySItDEmqVAhIx60= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4Nwi6NQNTYcnRVBD3g/5058yNqzeG1RJWvkYxn8oDJk=; b=VIv/MhDXGJLeq1xzGL3AYx0Oph5T1yi99+lsNdEqOoQcukW7hHlarWrKp+boc2zrSv cN0h5QKPeOfijb3y/3rRtqQqn/M0Z210j0JOdSmdXIvPbiILzT4gZoXbhjI+SblDAebh yVTdaehWHfE/22E0dvni/y2GiU0jbcJ7XrDqDnQh4ytSaS27L1EH5poX5EYFcGPqN9tD Lb1vEviTe7HHDAiZwP3OA/lgT1HOXO6/Puw59R/Be1bhcp7+V2aSr2TVRkUiAWCzaUkm 5afxJnbhoC+DEK1MlMQxrjhv54CXsqn4a41nJ8txGLGZidz2ZdFgoOgiyMbpHcXMvPJM ytDQ== X-Gm-Message-State: AD7BkJKBZEQngMpp6FxEKqb0kV3gRBFmJBXrT35HBAl1jVa1hdEqYw8TiI6JjAgm9kUMGF/B X-Received: by 10.98.9.27 with SMTP id e27mr24419007pfd.59.1456772091398; Mon, 29 Feb 2016 10:54:51 -0800 (PST) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id l24sm39783355pfb.73.2016.02.29.10.54.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 29 Feb 2016 10:54:50 -0800 (PST) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, alexander.shishkin@linux.intel.com Subject: [PATCH 6/8] coresight: etm4x: moving etm_drvdata::enable to atomic field Date: Mon, 29 Feb 2016 11:54:25 -0700 Message-Id: <1456772067-18085-7-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1456772067-18085-1-git-send-email-mathieu.poirier@linaro.org> References: <1456772067-18085-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Similarly to ETMv3, moving etmv4_drvdata::enable to an atomic type that gives the 'mode' of a tracer and prevents multiple, simultanious access by different subsystems. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x.c | 69 +++++++++++++++++++++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 5 +- 2 files changed, 63 insertions(+), 11 deletions(-) -- 2.1.4 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 4b83a753256b..738acee18967 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "coresight-etm4x.h" @@ -77,7 +78,7 @@ static int etm4_trace_id(struct coresight_device *csdev) unsigned long flags; int trace_id = -1; - if (!drvdata->enable) + if (!local_read(&drvdata->mode)) return drvdata->trcid; spin_lock_irqsave(&drvdata->spinlock, flags); @@ -189,8 +190,7 @@ static void etm4_enable_hw(void *info) dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu); } -static int etm4_enable(struct coresight_device *csdev, - struct perf_event_attr *attr, u32 mode) +static int etm4_enable_sysfs(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); int ret; @@ -205,18 +205,46 @@ static int etm4_enable(struct coresight_device *csdev, etm4_enable_hw, drvdata, 1); if (ret) goto err; - drvdata->enable = true; - drvdata->sticky_enable = true; + drvdata->sticky_enable = true; spin_unlock(&drvdata->spinlock); dev_info(drvdata->dev, "ETM tracing enabled\n"); return 0; + err: spin_unlock(&drvdata->spinlock); return ret; } +static int etm4_enable(struct coresight_device *csdev, + struct perf_event_attr *attr, u32 mode) +{ + int ret; + u32 val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); + + /* Someone is already using the tracer */ + if (val) + return -EBUSY; + + switch (mode) { + case CS_MODE_SYSFS: + ret = etm4_enable_sysfs(csdev); + break; + default: + ret = -EINVAL; + } + + /* The tracer didn't start */ + if (ret) + local_set(&drvdata->mode, CS_MODE_DISABLED); + + return ret; +} + static void etm4_disable_hw(void *info) { u32 control; @@ -239,7 +267,7 @@ static void etm4_disable_hw(void *info) dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu); } -static void etm4_disable(struct coresight_device *csdev) +static void etm4_disable_sysfs(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -257,7 +285,6 @@ static void etm4_disable(struct coresight_device *csdev) * ensures that register writes occur when cpu is powered. */ smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1); - drvdata->enable = false; spin_unlock(&drvdata->spinlock); put_online_cpus(); @@ -265,6 +292,30 @@ static void etm4_disable(struct coresight_device *csdev) dev_info(drvdata->dev, "ETM tracing disabled\n"); } +static void etm4_disable(struct coresight_device *csdev) +{ + u32 mode; + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + /* + * For as long as the tracer isn't disabled another entity can't + * change its status. As such we can read the status here without + * fearing it will change under us. + */ + mode = local_read(&drvdata->mode); + + switch (mode) { + case CS_MODE_DISABLED: + break; + case CS_MODE_SYSFS: + etm4_disable_sysfs(csdev); + break; + } + + if (mode) + local_set(&drvdata->mode, CS_MODE_DISABLED); +} + static const struct coresight_ops_source etm4_source_ops = { .cpu_id = etm4_cpu_id, .trace_id = etm4_trace_id, @@ -532,7 +583,7 @@ static int etm4_cpu_callback(struct notifier_block *nfb, unsigned long action, etmdrvdata[cpu]->os_unlock = true; } - if (etmdrvdata[cpu]->enable) + if (local_read(&etmdrvdata[cpu]->mode)) etm4_enable_hw(etmdrvdata[cpu]); spin_unlock(&etmdrvdata[cpu]->spinlock); break; @@ -545,7 +596,7 @@ static int etm4_cpu_callback(struct notifier_block *nfb, unsigned long action, case CPU_DYING: spin_lock(&etmdrvdata[cpu]->spinlock); - if (etmdrvdata[cpu]->enable) + if (local_read(&etmdrvdata[cpu]->mode)) etm4_disable_hw(etmdrvdata[cpu]); spin_unlock(&etmdrvdata[cpu]->spinlock); break; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 6ff499bfb2f2..f7748ae63451 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -13,6 +13,7 @@ #ifndef _CORESIGHT_CORESIGHT_ETM_H #define _CORESIGHT_CORESIGHT_ETM_H +#include #include #include "coresight-priv.h" @@ -290,6 +291,7 @@ struct etmv4_config { * @dev: The device entity associated to this component. * @csdev: Component vitals needed by the framework. * @spinlock: Only one at a time pls. + * @mode: This tracer's mode, i.e sysFS, Perf or disabled. * @cpu: The cpu this component is affined to. * @arch: ETM version number. * @nr_pe: The number of processing entity available for tracing. @@ -316,7 +318,6 @@ struct etmv4_config { * supported for the corresponding Exception level. * @ns_ex_level:In non-secure state, indicates whether instruction tracing is * supported for the corresponding Exception level. - * @enable: Is this ETM currently tracing. * @sticky_enable: true if ETM base configuration has been done. * @boot_enable:True if we should start tracing at boot time. * @os_unlock: True if access to management registers is allowed. @@ -346,6 +347,7 @@ struct etmv4_drvdata { struct device *dev; struct coresight_device *csdev; spinlock_t spinlock; + local_t mode; int cpu; u8 arch; u8 nr_pe; @@ -368,7 +370,6 @@ struct etmv4_drvdata { u8 ccitmin; u8 s_ex_level; u8 ns_ex_level; - bool enable; bool sticky_enable; bool boot_enable; bool os_unlock;