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[209.132.180.67]) by mx.google.com with ESMTP id sm10si5506844pab.78.2016.02.29.10.55.13; Mon, 29 Feb 2016 10:55:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753854AbcB2SzA (ORCPT + 30 others); Mon, 29 Feb 2016 13:55:00 -0500 Received: from mail-pf0-f182.google.com ([209.85.192.182]:34102 "EHLO mail-pf0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753764AbcB2Syy (ORCPT ); Mon, 29 Feb 2016 13:54:54 -0500 Received: by mail-pf0-f182.google.com with SMTP id 4so18585085pfd.1 for ; Mon, 29 Feb 2016 10:54:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aUqGK8wv5mIEcVPQ6zWV8ol9PnGy+YYewFoeS3J43bo=; b=Wo+5XfkWwZHtmZZ1mv3rw9Dnvno0XvNAdY8mWriSGif1zPjjuJjo8FsierF94BOxFP 9RztdfhRAWUMuc43eHMQ+UXeqMVcOtiHywrBmvmOVPI5AMapX8jt+vhfY/NlriDQB1GZ EkbwuuseFRh3tnVVL1Q1uGQdNWVargENUPUac= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aUqGK8wv5mIEcVPQ6zWV8ol9PnGy+YYewFoeS3J43bo=; b=BZ07u2dgMc1zMGC7aVYnLBxh/2NktM4faljC1YREot41zyNLeepguqQib9ZS9x9UB6 485P/7G5DAFSXHcCcNC0qCYfQBWwU1mt/2UwUrZYtO55NinKhYpu/dAFpv0V3vABNYMB Ju4XFmhbnPL1nmpj/ZLmD77qrLh52QTgXtdzJFYMs0Fp7YKpOMyfGxmB6ZuQo2yxGprX FvOZoa7JEum77hcVZ4mHbPDQ0BswJYGewS8No7zSC3hGsZJAKigCjTKC8n7sZaXsiX8L VmFuSlZykZ4o3Ln7ZZgiIe93gtSOgYMEUBitYJeXPJLIzPMREo64Ig+u+//I8eDSveMQ NyaA== X-Gm-Message-State: AD7BkJJJspBhsWcf30y0GaGQbVQ4ypceJVhlLxtQfUz2deKy/E0ZQyqESzt6TVdG+7B3Uu+a X-Received: by 10.98.79.28 with SMTP id d28mr23931575pfb.77.1456772093637; Mon, 29 Feb 2016 10:54:53 -0800 (PST) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id l24sm39783355pfb.73.2016.02.29.10.54.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 29 Feb 2016 10:54:53 -0800 (PST) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, alexander.shishkin@linux.intel.com Subject: [PATCH 8/8] coresight: etm4x: implementing the perf PMU API Date: Mon, 29 Feb 2016 11:54:27 -0700 Message-Id: <1456772067-18085-9-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1456772067-18085-1-git-send-email-mathieu.poirier@linaro.org> References: <1456772067-18085-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adding a set of API allowing the Perf core to treat ETMv4 tracers like other PMUs. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/Makefile | 5 +- drivers/hwtracing/coresight/coresight-etm4x.c | 85 +++++++++++++++++++++++++-- 2 files changed, 82 insertions(+), 8 deletions(-) -- 2.1.4 diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 637ca978cd05..1d0e32c7dbe4 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -1,7 +1,7 @@ # # Makefile for CoreSight drivers. # -obj-$(CONFIG_CORESIGHT) += coresight.o +obj-$(CONFIG_CORESIGHT) += coresight.o coresight-etm-perf.o obj-$(CONFIG_OF) += of_coresight.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o @@ -9,8 +9,7 @@ obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \ coresight-replicator.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o \ - coresight-etm3x-sysfs.o \ - coresight-etm-perf.o + coresight-etm3x-sysfs.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \ coresight-etm4x-sysfs.o obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 743c34b92a80..8bd400cce904 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -32,12 +32,14 @@ #include #include #include +#include #include #include #include #include #include "coresight-etm4x.h" +#include "coresight-etm-perf.h" static int boot_enable; module_param_named(boot_enable, boot_enable, int, S_IRUGO); @@ -45,6 +47,7 @@ module_param_named(boot_enable, boot_enable, int, S_IRUGO); /* The number of ETMv4 currently registered */ static int etm4_count; static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; +static void etm4_set_default(struct etmv4_config *config); static void etm4_os_unlock(struct etmv4_drvdata *drvdata) { @@ -190,6 +193,58 @@ static void etm4_enable_hw(void *info) dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu); } +static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, + struct perf_event_attr *attr) +{ + struct etmv4_config *config = &drvdata->config; + + if (!attr) + return -EINVAL; + + /* Clear configuration from previous run */ + memset(config, 0, sizeof(struct etmv4_config)); + + if (attr->exclude_kernel) + config->mode = ETM_MODE_EXCL_KERN; + + if (attr->exclude_user) + config->mode = ETM_MODE_EXCL_USER; + + /* Always start from the default config */ + etm4_set_default(config); + + /* + * By default the tracers are configured to trace the whole address + * range. Narrow the field only if requested by user space. + */ + if (config->mode) + etm4_config_trace_mode(config); + + /* Go from generic option to ETMv4 specifics */ + if (attr->config & BIT(ETM_OPT_CYCACC)) + config->cfg |= ETMv4_MODE_CYCACC; + if (attr->config & BIT(ETM_OPT_TS)) + config->cfg |= ETMv4_MODE_TIMESTAMP; + + return 0; +} + +static int etm4_enable_perf(struct coresight_device *csdev, + struct perf_event_attr *attr) +{ + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) + return -EINVAL; + + /* Configure the tracer based on the session's specifics */ + etm4_parse_event_config(drvdata, attr); + /* And enable it */ + etm4_enable_hw(drvdata); + + return 0; +} + static int etm4_enable_sysfs(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -234,6 +289,9 @@ static int etm4_enable(struct coresight_device *csdev, case CS_MODE_SYSFS: ret = etm4_enable_sysfs(csdev); break; + case CS_MODE_PERF: + ret = etm4_enable_perf(csdev, attr); + break; default: ret = -EINVAL; } @@ -267,6 +325,17 @@ static void etm4_disable_hw(void *info) dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu); } +static int etm4_disable_perf(struct coresight_device *csdev) +{ + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) + return -EINVAL; + + etm4_disable_hw(drvdata); + return 0; +} + static void etm4_disable_sysfs(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -310,6 +379,9 @@ static void etm4_disable(struct coresight_device *csdev) case CS_MODE_SYSFS: etm4_disable_sysfs(csdev); break; + case CS_MODE_PERF: + etm4_disable_perf(csdev); + break; } if (mode) @@ -709,8 +781,6 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) etm4_init_trace_id(drvdata); etm4_set_default(&drvdata->config); - pm_runtime_put(&adev->dev); - desc->type = CORESIGHT_DEV_TYPE_SOURCE; desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; desc->ops = &etm4_cs_ops; @@ -720,9 +790,16 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) drvdata->csdev = coresight_register(desc); if (IS_ERR(drvdata->csdev)) { ret = PTR_ERR(drvdata->csdev); - goto err_coresight_register; + goto err_arch_supported; } + ret = etm_perf_symlink(drvdata->csdev, true); + if (ret) { + coresight_unregister(drvdata->csdev); + goto err_arch_supported; + } + + pm_runtime_put(&adev->dev); dev_info(dev, "%s initialized\n", (char *)id->data); if (boot_enable) { @@ -733,8 +810,6 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) return 0; err_arch_supported: - pm_runtime_put(&adev->dev); -err_coresight_register: if (--etm4_count == 0) unregister_hotcpu_notifier(&etm4_cpu_notifier); return ret;