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c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:To:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=qcYMGNSXvPp9qAwJGwYgmBCH+dLWGVIkD8/OqYEtRjQ=; b=zXgqRKSQ6+rUkS45Qg9sI7qcwUoDN57SIUAmr5EONnF5A0TjMAhPqwBSkCSLpIAYsgNjRj37Xx8QbGLwXfEuIFFgR+67sRwsPWfasxW+EahkLstPdZQwtVHJIld8FB5wwAgFf+c4RgoWnK6H8ARzIP3WMWu0DIQOTpRsbGtIPMY= Authentication-Results: redhat.com; dkim=none (message not signed) header.d=none; redhat.com; dmarc=none action=none header.from=amd.com; Received: from localhost.localdomain (124.121.8.20) by BY1PR12MB0437.namprd12.prod.outlook.com (10.162.147.139) with Microsoft SMTP Server (TLS) id 15.1.443.12; Fri, 18 Mar 2016 06:11:36 +0000 From: Suravee Suthikulpanit To: , , , , , CC: , , , , Suravee Suthikulpanit , Suravee Suthikulpanit Subject: [PART1 RFC v3 11/12] svm: Do not intercept CR8 when enable AVIC Date: Fri, 18 Mar 2016 01:09:47 -0500 Message-ID: <1458281388-14452-12-git-send-email-Suravee.Suthikulpanit@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1458281388-14452-1-git-send-email-Suravee.Suthikulpanit@amd.com> References: <1458281388-14452-1-git-send-email-Suravee.Suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [124.121.8.20] X-ClientProxiedBy: SG2PR04CA0047.apcprd04.prod.outlook.com (25.169.49.143) To BY1PR12MB0437.namprd12.prod.outlook.com (25.162.147.139) X-MS-Office365-Filtering-Correlation-Id: 25f6607b-9aef-47ad-e40e-08d34ef42e66 X-Microsoft-Exchange-Diagnostics: 1; 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BY1PR12MB0437; 5:UQw24OOL/sAvXpkFQppq+/UFQw5/flTvQoV3jB/0lLWpWtBvkiaNdEOMd+O2zWtGWWBVhrvIy0HDYa4qGNf9CwJyRIyDql8W0KtUriiHIM0qU+hwg9H7BjgNRLm86RZnu2qR1OVoMzlt6Xst+4IS1A==; 24:pb3Rq/vrQN7+QehtbNaUa6T64J07J6t+svDSxUVy/0eh+4pXzcK3EVM6QSprOJ/v3rTZ+qb8bERDeIx9qSEn8N/CaPSZH2jSjQjrquAtxGA=; 20:0pL9z3Q8mAaCy0KytZ2SiOfPP218aeRUjVkKem7E8UMalCk+TL5099ZpdL75YFIsLlGjWS8nINm0z+YyNop4tmc6k1Zv0cg49C5vT/+1sNRw5QakncMrXRSiHODrglJCDVWVldWcJ3WUOJu9k8Sl4ZJlHQOyDXHO7faP2EpK5c0hqMzWSrkTLVLAa67NMXai7xJeT58Gjarow8jpPLlkw1UmS30XVE1e9KaobzYUMkIgExNzNfVfzcB3ZNMxfzLA X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2016 06:11:36.4976 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR12MB0437 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When enable AVIC: * Do not intercept CR8 since this should be handled by AVIC HW. * Also update TPR in APIC backing page when syncing CR8 before VMRUN Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) -- 1.9.1 diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index ba84d57..d5418c3 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -984,6 +984,8 @@ static __init int svm_hardware_setup(void) if (avic) { printk(KERN_INFO "kvm: AVIC enabled\n"); + + svm_x86_ops.update_cr8_intercept = NULL; } else { svm_x86_ops.deliver_posted_interrupt = NULL; } @@ -1097,7 +1099,8 @@ static void init_vmcb(struct vcpu_svm *svm) set_cr_intercept(svm, INTERCEPT_CR0_WRITE); set_cr_intercept(svm, INTERCEPT_CR3_WRITE); set_cr_intercept(svm, INTERCEPT_CR4_WRITE); - set_cr_intercept(svm, INTERCEPT_CR8_WRITE); + if (!svm_vcpu_avic_enabled(svm)) + set_cr_intercept(svm, INTERCEPT_CR8_WRITE); set_dr_intercepts(svm); @@ -4080,7 +4083,8 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) { struct vcpu_svm *svm = to_svm(vcpu); - if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) + if ((is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) || + svm_vcpu_avic_enabled(svm)) return; clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); @@ -4271,9 +4275,12 @@ static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) return; - cr8 = kvm_get_cr8(vcpu); + cr8 = kvm_get_cr8(vcpu) & V_TPR_MASK; svm->vmcb->control.int_ctl &= ~V_TPR_MASK; - svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; + svm->vmcb->control.int_ctl |= cr8; + + if (svm_vcpu_avic_enabled(svm)) + kvm_lapic_set_reg(svm->vcpu.arch.apic, APIC_TASKPRI, (u32)cr8 << 4); } static void svm_complete_interrupts(struct vcpu_svm *svm)