From patchwork Fri Apr 22 10:41:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 66433 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp641624qge; Fri, 22 Apr 2016 03:42:20 -0700 (PDT) X-Received: by 10.98.32.211 with SMTP id m80mr27373069pfj.3.1461321740762; Fri, 22 Apr 2016 03:42:20 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id wg1si7111815pab.52.2016.04.22.03.42.20; Fri, 22 Apr 2016 03:42:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752164AbcDVKmS (ORCPT + 29 others); Fri, 22 Apr 2016 06:42:18 -0400 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:40315 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751712AbcDVKmR (ORCPT ); Fri, 22 Apr 2016 06:42:17 -0400 Received: from edgewater-inn.cambridge.arm.com (edgewater-inn.cambridge.arm.com [10.1.203.121]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id u3MAfpWr019587; Fri, 22 Apr 2016 11:41:51 +0100 (BST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 047061AE0E13; Fri, 22 Apr 2016 11:41:51 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: Will Deacon , "Paul E. McKenney" , Peter Zijlstra Subject: [PATCH] documentation: ACQUIRE applies to loads, RELEASE applies to stores Date: Fri, 22 Apr 2016 11:41:49 +0100 Message-Id: <1461321709-16619-1-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For compound atomics performing both a load and a store operation, make it clear that _acquire and _release variants refer only to the load and store portions of compound atomic. For example, xchg_acquire is an xchg operation where the load takes on ACQUIRE semantics. Cc: Paul E. McKenney Cc: Peter Zijlstra Signed-off-by: Will Deacon --- Documentation/memory-barriers.txt | 5 +++++ 1 file changed, 5 insertions(+) -- 2.1.4 diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 3729cbe60e41..05f8011011be 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -464,6 +464,11 @@ And a couple of implicit varieties: This means that ACQUIRE acts as a minimal "acquire" operation and RELEASE acts as a minimal "release" operation. +A subset of the atomic operations described in atomic_ops.txt have ACQUIRE +and RELEASE variants in addition to fully-ordered and relaxed (no barrier +semantics) definitions. For compound atomics performing both a load and a +store, ACQUIRE semantics apply only to the load and RELEASE semantics apply +only to the store portion of the operation. Memory barriers are only required where there's a possibility of interaction between two CPUs or between a CPU and a device. If it can be guaranteed that