From patchwork Tue Apr 26 22:10:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 66742 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp1858378qge; Tue, 26 Apr 2016 15:12:22 -0700 (PDT) X-Received: by 10.98.101.199 with SMTP id z190mr7084181pfb.1.1461708742415; Tue, 26 Apr 2016 15:12:22 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 145si6489570pfy.175.2016.04.26.15.12.22; Tue, 26 Apr 2016 15:12:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752780AbcDZWMT (ORCPT + 29 others); Tue, 26 Apr 2016 18:12:19 -0400 Received: from mail-io0-f170.google.com ([209.85.223.170]:34152 "EHLO mail-io0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753123AbcDZWLE (ORCPT ); Tue, 26 Apr 2016 18:11:04 -0400 Received: by mail-io0-f170.google.com with SMTP id 190so24197825iow.1 for ; Tue, 26 Apr 2016 15:11:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XPrqA0ijOTHNl+j4mSs7V1ve/1Mdn42p//yo8+7lh1Y=; b=WGXK/IvQA24NVrLKk9dKgiyrzEW0TsGMJgz9PKSn2puJpR7p3ADQBZRq1MzMTAn+xZ S7xMn/3L8Mj4va+P0wjotvXhmfFOglhWDTgj/wvnF/kEv2d9vk5Nl9J2yOSzVryC9Mpj gNQSpkaTZlC+Ia3uRrklB69Dy6H5HdGQp8cUo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XPrqA0ijOTHNl+j4mSs7V1ve/1Mdn42p//yo8+7lh1Y=; b=aWsAgtJYZ9TzStp2HjIO2RlreNaIcSPxs9q7ZS85IWhrdJiVgdkRxz1hyQbvM9Kw4n jmipIj9BcmdiHgLvATwpjnr/P4wKmWvQXVKlvTRN66WtmGv5BqpfEleFvKfl1C+WJtC4 QDkSApV4DaQKu34IZy9dlLT0mRVINV3hJc9ZqbZM2X0rIpGF8+7bMn22sJsRQz1hV/wg Bh5riufGe/iZT22tLMvcORLqUQdrpLfHa0xlxxN6B91WkoyI3P8v6/48XEdLMTsDGX4A lyjQthOwgJFs6e6zakS3f6YT/BCEANCefQwHkUP8oGnK8l33sZkep40XtUmrvj+fAgwo 2MuA== X-Gm-Message-State: AOPr4FWqki5krC/vTKvg8SgZex+6K3RXcbkb7LoW1ztQygT8pWFAtkJSI3ub83TBCbs3kP5N X-Received: by 10.107.137.166 with SMTP id t38mr6416244ioi.31.1461708663234; Tue, 26 Apr 2016 15:11:03 -0700 (PDT) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id zd17sm2684818igc.8.2016.04.26.15.11.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Apr 2016 15:11:02 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org, Suzuki.Poulose@arm.com Cc: linux-kernel@vger.kernel.org Subject: [PATCH V4 14/18] coresight: tmc: keep track of memory width Date: Tue, 26 Apr 2016 16:10:30 -0600 Message-Id: <1461708634-6327-15-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1461708634-6327-1-git-send-email-mathieu.poirier@linaro.org> References: <1461708634-6327-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Accessing the HW configuration register each time the memory width is needed simply doesn't make sense. It is much more efficient to read the value once and keep a reference for later use. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 14 +--------- drivers/hwtracing/coresight/coresight-tmc.c | 34 +++++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 10 +++++--- 3 files changed, 41 insertions(+), 17 deletions(-) -- 2.5.0 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index b11c52be54a9..ba3384781f71 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -41,25 +41,13 @@ void tmc_etb_enable_hw(struct tmc_drvdata *drvdata) static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) { - enum tmc_mem_intf_width memwidth; - u8 memwords; char *bufp; u32 read_data; int i; - memwidth = BMVAL(readl_relaxed(drvdata->base + CORESIGHT_DEVID), 8, 10); - if (memwidth == TMC_MEM_INTF_WIDTH_32BITS) - memwords = 1; - else if (memwidth == TMC_MEM_INTF_WIDTH_64BITS) - memwords = 2; - else if (memwidth == TMC_MEM_INTF_WIDTH_128BITS) - memwords = 4; - else - memwords = 8; - bufp = drvdata->buf; while (1) { - for (i = 0; i < memwords; i++) { + for (i = 0; i < drvdata->memwidth; i++) { read_data = readl_relaxed(drvdata->base + TMC_RRD); if (read_data == 0xFFFFFFFF) return; diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index ae7525a2b94a..9e02ac963cd0 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -186,6 +186,39 @@ static const struct file_operations tmc_fops = { .llseek = no_llseek, }; +static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid) +{ + enum tmc_mem_intf_width memwidth; + + /* + * Excerpt from the TRM: + * + * DEVID::MEMWIDTH[10:8] + * 0x2 Memory interface databus is 32 bits wide. + * 0x3 Memory interface databus is 64 bits wide. + * 0x4 Memory interface databus is 128 bits wide. + * 0x5 Memory interface databus is 256 bits wide. + */ + switch (BMVAL(devid, 8, 10)) { + case 0x2: + memwidth = TMC_MEM_INTF_WIDTH_32BITS; + break; + case 0x3: + memwidth = TMC_MEM_INTF_WIDTH_64BITS; + break; + case 0x4: + memwidth = TMC_MEM_INTF_WIDTH_128BITS; + break; + case 0x5: + memwidth = TMC_MEM_INTF_WIDTH_256BITS; + break; + default: + memwidth = 0; + } + + return memwidth; +} + #define coresight_tmc_simple_func(name, offset) \ coresight_simple_func(struct tmc_drvdata, name, offset) @@ -299,6 +332,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); drvdata->config_type = BMVAL(devid, 6, 7); + drvdata->memwidth = tmc_get_memwidth(devid); if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { if (np) diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 94bc034d3b98..c5d06fd57fa8 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -81,10 +81,10 @@ enum tmc_mode { }; enum tmc_mem_intf_width { - TMC_MEM_INTF_WIDTH_32BITS = 0x2, - TMC_MEM_INTF_WIDTH_64BITS = 0x3, - TMC_MEM_INTF_WIDTH_128BITS = 0x4, - TMC_MEM_INTF_WIDTH_256BITS = 0x5, + TMC_MEM_INTF_WIDTH_32BITS = 1, + TMC_MEM_INTF_WIDTH_64BITS = 2, + TMC_MEM_INTF_WIDTH_128BITS = 4, + TMC_MEM_INTF_WIDTH_256BITS = 8, }; /** @@ -100,6 +100,7 @@ enum tmc_mem_intf_width { * @size: @buf size. * @mode: how this TMC is being used. * @config_type: TMC variant, must be of type @tmc_config_type. + * @memwidth: width of the memory interface databus, in bytes. * @trigger_cntr: amount of words to store after a trigger. */ struct tmc_drvdata { @@ -115,6 +116,7 @@ struct tmc_drvdata { u32 size; local_t mode; enum tmc_config_type config_type; + enum tmc_mem_intf_width memwidth; u32 trigger_cntr; };