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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id zd17sm2684818igc.8.2016.04.26.15.10.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 26 Apr 2016 15:10:46 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org, Suzuki.Poulose@arm.com Cc: linux-kernel@vger.kernel.org Subject: [PATCH V4 06/18] coresight: tmc: cleaning up header file Date: Tue, 26 Apr 2016 16:10:22 -0600 Message-Id: <1461708634-6327-7-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1461708634-6327-1-git-send-email-mathieu.poirier@linaro.org> References: <1461708634-6327-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch first move the TMC_STS_TMCREADY_BIT and TMC_FFCR_FLUSHMAN_BIT defines to their respective section. It also removes TMC_FFCR_FLUSHMAN, since the same result can easily be obtained using the BIT() macro. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-tmc.c | 2 +- drivers/hwtracing/coresight/coresight-tmc.h | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) -- 2.5.0 diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index f9a6624ab531..07e2809d832b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -50,7 +50,7 @@ static void tmc_flush_and_stop(struct tmc_drvdata *drvdata) ffcr = readl_relaxed(drvdata->base + TMC_FFCR); ffcr |= TMC_FFCR_STOP_ON_FLUSH; writel_relaxed(ffcr, drvdata->base + TMC_FFCR); - ffcr |= TMC_FFCR_FLUSHMAN; + ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT); writel_relaxed(ffcr, drvdata->base + TMC_FFCR); /* Ensure flush completes */ if (coresight_timeout(drvdata->base, diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 49718b4a9788..5a60830c8db5 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -49,6 +49,7 @@ /* TMC_CTL - 0x020 */ #define TMC_CTL_CAPT_EN BIT(0) /* TMC_STS - 0x00C */ +#define TMC_STS_TMCREADY_BIT 2 #define TMC_STS_TRIGGERED BIT(1) /* TMC_AXICTL - 0x110 */ #define TMC_AXICTL_PROT_CTL_B0 BIT(0) @@ -56,16 +57,14 @@ #define TMC_AXICTL_SCT_GAT_MODE BIT(7) #define TMC_AXICTL_WR_BURST_16 0xF00 /* TMC_FFCR - 0x304 */ +#define TMC_FFCR_FLUSHMAN_BIT 6 #define TMC_FFCR_EN_FMT BIT(0) #define TMC_FFCR_EN_TI BIT(1) #define TMC_FFCR_FON_FLIN BIT(4) #define TMC_FFCR_FON_TRIG_EVT BIT(5) -#define TMC_FFCR_FLUSHMAN BIT(6) #define TMC_FFCR_TRIGON_TRIGIN BIT(8) #define TMC_FFCR_STOP_ON_FLUSH BIT(12) -#define TMC_STS_TMCREADY_BIT 2 -#define TMC_FFCR_FLUSHMAN_BIT 6 enum tmc_config_type { TMC_CONFIG_TYPE_ETB,