From patchwork Tue May 10 09:50:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 67415 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp2033044qge; Tue, 10 May 2016 02:52:27 -0700 (PDT) X-Received: by 10.66.43.241 with SMTP id z17mr13456964pal.18.1462873947826; Tue, 10 May 2016 02:52:27 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id wl8si2047146pab.33.2016.05.10.02.52.27; Tue, 10 May 2016 02:52:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752286AbcEJJwG (ORCPT + 29 others); Tue, 10 May 2016 05:52:06 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:34982 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752219AbcEJJwC (ORCPT ); Tue, 10 May 2016 05:52:02 -0400 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id u4A9o2q8001762; Tue, 10 May 2016 18:50:18 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com u4A9o2q8001762 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1462873819; bh=D0jlL5ksUv8Zqwa2H/D1Ogu8shhs4QcDBQ349MRxMjk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vYpRtb6Y8Aj/MnJWoZXdxsLxLG6Na3FEGhbEDpbY9AtgIDCdxK2xSoAOa8LxPkH6K Scx/ml5dbfPEbRy6tW9Nr/bVPToHK/A4vb2eEpB3g1T/7I4mpFJ0gmSK62zOgnOIBk 7zSi9QRjVS3gCy23mVb99v4CToMoIoMf2v5jqCoceXmlOSBouwlZx/pZy/7YEh1g/S bAE2MiNgjovIiU3p147egjHwSEM7A/jtdH9F+ZmxjOWwDSPLMyZenjFIyK+FN1b5LQ 68rbVaagb9whcxDARHAtbKgTDsM4MA/SHeteb3KyHnmflTLnodB+RqGtCZSifwyiIw C1qYYbD049dyQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-clk@vger.kernel.org, Arnd Bergmann , Philipp Zabel Cc: Masahiro Yamada , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 11/21] clk: uniphier: add clock driver for Peripheral block on UniPhier SoCs Date: Tue, 10 May 2016 18:50:52 +0900 Message-Id: <1462873862-30940-12-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462873862-30940-1-git-send-email-yamada.masahiro@socionext.com> References: <1462873862-30940-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series is just for review. Please do not apply this patch. Signed-off-by: Masahiro Yamada --- drivers/clk/uniphier/Kconfig | 4 + drivers/clk/uniphier/Makefile | 1 + drivers/clk/uniphier/clk-uniphier-peri.c | 133 +++++++++++++++++++++++++++++++ 3 files changed, 138 insertions(+) create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c -- 1.9.1 diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig index 895c4a0..08edaf8 100644 --- a/drivers/clk/uniphier/Kconfig +++ b/drivers/clk/uniphier/Kconfig @@ -38,4 +38,8 @@ config CLK_UNIPHIER_MIO tristate "Clock driver for UniPhier Media I/O block" default y +config CLK_UNIPHIER_PERI + tristate "Clock driver for UniPhier Peripheral block" + default y + endif diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile index ae71f04..a69d6fe 100644 --- a/drivers/clk/uniphier/Makefile +++ b/drivers/clk/uniphier/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_CLK_UNIPHIER_LD11) += clk-uniphier-ld11.o obj-$(CONFIG_CLK_UNIPHIER_LD20) += clk-uniphier-ld20.o obj-$(CONFIG_CLK_UNIPHIER_MIO) += clk-uniphier-mio.o +obj-$(CONFIG_CLK_UNIPHIER_PERI) += clk-uniphier-peri.o diff --git a/drivers/clk/uniphier/clk-uniphier-peri.c b/drivers/clk/uniphier/clk-uniphier-peri.c new file mode 100644 index 0000000..e5510f5 --- /dev/null +++ b/drivers/clk/uniphier/clk-uniphier-peri.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include "clk-uniphier.h" + +#define UNIPHIER_PERI_CLK_UART(ch, index) \ + { \ + .name = "uart" #ch, \ + .type = UNIPHIER_CLK_TYPE_GATE, \ + .output_index = (index), \ + .data.gate = { \ + .parent_name = "uart", \ + .reg = 0x24, \ + .mask = BIT(19 + ch), \ + .enable_val = BIT(19 + ch), \ + }, \ + } + +#define UNIPHIER_PERI_CLK_I2C_COMMON \ + { \ + .name = "i2c-common", \ + .type = UNIPHIER_CLK_TYPE_GATE, \ + .output_index = -1, \ + .data.gate = { \ + .parent_name = "i2c", \ + .reg = 0x20, \ + .mask = BIT(1), \ + .enable_val = BIT(1), \ + }, \ + } + +#define UNIPHIER_PERI_CLK_I2C(ch, index) \ + { \ + .name = "i2c" #ch, \ + .type = UNIPHIER_CLK_TYPE_GATE, \ + .output_index = (index), \ + .data.gate = { \ + .parent_name = "i2c-common", \ + .reg = 0x24, \ + .mask = BIT(5 + ch), \ + .enable_val = BIT(5 + ch), \ + }, \ + } + +#define UNIPHIER_PERI_CLK_FI2C(ch, index) \ + { \ + .name = "fi2c" #ch, \ + .type = UNIPHIER_CLK_TYPE_GATE, \ + .output_index = (index), \ + .data.gate = { \ + .parent_name = "fi2c", \ + .reg = 0x24, \ + .mask = BIT(24 + ch), \ + .enable_val = BIT(24 + ch), \ + }, \ + } + +static const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = { + UNIPHIER_PERI_CLK_UART(0, 0), + UNIPHIER_PERI_CLK_UART(1, 1), + UNIPHIER_PERI_CLK_UART(2, 2), + UNIPHIER_PERI_CLK_UART(3, 3), + UNIPHIER_PERI_CLK_I2C_COMMON, + UNIPHIER_PERI_CLK_I2C(0, 4), + UNIPHIER_PERI_CLK_I2C(1, 5), + UNIPHIER_PERI_CLK_I2C(2, 6), + UNIPHIER_PERI_CLK_I2C(3, 7), + UNIPHIER_PERI_CLK_I2C(4, 8), + { /* sentinel */ } +}; + +static int uniphier_ld4_peri_clk_probe(struct platform_device *pdev) +{ + return uniphier_clk_probe(pdev, uniphier_ld4_peri_clk_data); +} + +static struct platform_driver uniphier_ld4_peri_clk_driver = { + .probe = uniphier_ld4_peri_clk_probe, + .remove = uniphier_clk_remove, + .driver = { + .name = "uniphier-ld4-peri-clk", + }, +}; +module_platform_driver(uniphier_ld4_peri_clk_driver); + +static const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = { + UNIPHIER_PERI_CLK_UART(0, 0), + UNIPHIER_PERI_CLK_UART(1, 1), + UNIPHIER_PERI_CLK_UART(2, 2), + UNIPHIER_PERI_CLK_UART(3, 3), + UNIPHIER_PERI_CLK_FI2C(0, 4), + UNIPHIER_PERI_CLK_FI2C(1, 5), + UNIPHIER_PERI_CLK_FI2C(2, 6), + UNIPHIER_PERI_CLK_FI2C(3, 7), + UNIPHIER_PERI_CLK_FI2C(4, 8), + UNIPHIER_PERI_CLK_FI2C(5, 9), + UNIPHIER_PERI_CLK_FI2C(6, 10), + { /* sentinel */ } +}; + +static int uniphier_pro4_peri_clk_probe(struct platform_device *pdev) +{ + return uniphier_clk_probe(pdev, uniphier_pro4_peri_clk_data); +} + +static struct platform_driver uniphier_pro4_peri_clk_driver = { + .probe = uniphier_pro4_peri_clk_probe, + .remove = uniphier_clk_remove, + .driver = { + .name = "uniphier-pro4-peri-clk", + }, +}; +module_platform_driver(uniphier_pro4_peri_clk_driver); + +MODULE_AUTHOR("Masahiro Yamada "); +MODULE_DESCRIPTION("UniPhier Peripheral Clock Driver"); +MODULE_LICENSE("GPL");