From patchwork Fri Jun 10 15:19:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 69789 Delivered-To: patch@linaro.org Received: by 10.140.106.246 with SMTP id e109csp349641qgf; Fri, 10 Jun 2016 08:20:01 -0700 (PDT) X-Received: by 10.107.17.31 with SMTP id z31mr4918568ioi.150.1465572001265; Fri, 10 Jun 2016 08:20:01 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y63si13565225pfy.97.2016.06.10.08.20.00; Fri, 10 Jun 2016 08:20:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753186AbcFJPT7 (ORCPT + 30 others); Fri, 10 Jun 2016 11:19:59 -0400 Received: from foss.arm.com ([217.140.101.70]:39121 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752578AbcFJPT5 (ORCPT ); Fri, 10 Jun 2016 11:19:57 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C99F8F; Fri, 10 Jun 2016 08:20:33 -0700 (PDT) Received: from e106634-lin.cambridge.arm.com (e106634-lin.cambridge.arm.com [10.1.209.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A60553F246; Fri, 10 Jun 2016 08:19:55 -0700 (PDT) From: Suzuki K Poulose To: catalin.marinas@arm.com, will.deacon@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, steve.capper@linaro.org, Mark Rutland , "Suzuki K. Poulose" Subject: [PATCH] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs Date: Fri, 10 Jun 2016 16:19:44 +0100 Message-Id: <1465571984-18776-1-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Steve Capper It can be useful for JIT software to be aware of MIDR_EL1 and REVIDR_EL1 to ascertain the presence of any core errata that could affect codegen. This patch exposes these registers through sysfs: /sys/devices/system/cpu/cpu$ID/identification/midr /sys/devices/system/cpu/cpu$ID/identification/revidr where $ID is the cpu number. For big.LITTLE systems, one can have a mixture of cores (e.g. Cortex A53 and Cortex A57), thus all CPUs need to be enumerated. If the kernel does not have valid information to populate these entries with, an empty string is returned to userspace. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Signed-off-by: Steve Capper [ Return error for access to !present CPU registers ] Signed-off-by: Suzuki K. Poulose --- Changes since V2: - Fix errno for failures (Spotted-by: Russell King) - Roll back, if we encounter a missing cpu device - Return error for access to registers of CPUs not present. --- arch/arm64/include/asm/cpu.h | 1 + arch/arm64/kernel/cpuinfo.c | 69 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) -- 1.9.1 diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index 13a6103..116a382 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -29,6 +29,7 @@ struct cpuinfo_arm64 { u32 reg_cntfrq; u32 reg_dczid; u32 reg_midr; + u32 reg_revidr; u64 reg_id_aa64dfr0; u64 reg_id_aa64dfr1; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index c173d32..c2d0c42 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -212,6 +212,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_ctr = read_cpuid_cachetype(); info->reg_dczid = read_cpuid(DCZID_EL0); info->reg_midr = read_cpuid_id(); + info->reg_revidr = read_cpuid(REVIDR_EL1); info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); @@ -264,3 +265,71 @@ void __init cpuinfo_store_boot_cpu(void) boot_cpu_data = *info; init_cpu_features(&boot_cpu_data); } + +#define CPUINFO_ATTR_RO(_name) \ + static ssize_t show_##_name (struct device *dev, \ + struct device_attribute *attr, char *buf) \ + { \ + struct cpuinfo_arm64 *info = &per_cpu(cpu_data, dev->id); \ + if (!cpu_present(dev->id)) \ + return -ENODEV; \ + \ + if (info->reg_midr) \ + return sprintf(buf, "0x%016x\n", info->reg_##_name); \ + else \ + return 0; \ + } \ + static DEVICE_ATTR(_name, 0444, show_##_name, NULL) + +CPUINFO_ATTR_RO(midr); +CPUINFO_ATTR_RO(revidr); + +static struct attribute *cpuregs_attrs[] = { + &dev_attr_midr.attr, + &dev_attr_revidr.attr, + NULL +}; + +static struct attribute_group cpuregs_attr_group = { + .attrs = cpuregs_attrs, + .name = "identification" +}; + +static int __init cpuinfo_regs_init(void) +{ + int cpu, finalcpu, ret; + struct device *dev; + + for_each_present_cpu(cpu) { + dev = get_cpu_device(cpu); + + if (!dev) { + ret = -ENODEV; + break; + } + + ret = sysfs_create_group(&dev->kobj, &cpuregs_attr_group); + if (ret) + break; + } + + if (!ret) + return 0; + /* + * We were unable to put down sysfs groups for all the CPUs, revert + * all the groups we have placed down s.t. none are visible. + * Otherwise we could give a misleading picture of what's present. + */ + finalcpu = cpu; + for_each_present_cpu(cpu) { + if (cpu == finalcpu) + break; + dev = get_cpu_device(cpu); + if (dev) + sysfs_remove_group(&dev->kobj, &cpuregs_attr_group); + } + + return ret; +} + +device_initcall(cpuinfo_regs_init);