From patchwork Thu Jun 16 13:28:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 70189 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp263155qgy; Thu, 16 Jun 2016 06:29:11 -0700 (PDT) X-Received: by 10.98.65.209 with SMTP id g78mr5136211pfd.93.1466083751311; Thu, 16 Jun 2016 06:29:11 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d62si6071719pfd.93.2016.06.16.06.29.10; Thu, 16 Jun 2016 06:29:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754561AbcFPN3I (ORCPT + 30 others); Thu, 16 Jun 2016 09:29:08 -0400 Received: from foss.arm.com ([217.140.101.70]:43750 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754219AbcFPN3F (ORCPT ); Thu, 16 Jun 2016 09:29:05 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 89AA02A2; Thu, 16 Jun 2016 06:29:46 -0700 (PDT) Received: from e106634-lin.cambridge.arm.com (e106634-lin.cambridge.arm.com [10.1.209.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4FC323F213; Thu, 16 Jun 2016 06:29:03 -0700 (PDT) From: Suzuki K Poulose To: catalin.marinas@arm.com, will.deacon@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, steve.capper@linaro.org, linux@arm.linux.org.uk, Mark Rutland , "Suzuki K. Poulose" Subject: [PATCH v5] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs Date: Thu, 16 Jun 2016 14:28:50 +0100 Message-Id: <1466083730-11786-1-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Steve Capper It can be useful for JIT software to be aware of MIDR_EL1 and REVIDR_EL1 to ascertain the presence of any core errata that could affect codegen. This patch exposes these registers through sysfs: /sys/devices/system/cpu/cpu$ID/identification/midr /sys/devices/system/cpu/cpu$ID/identification/revidr where $ID is the cpu number. For big.LITTLE systems, one can have a mixture of cores (e.g. Cortex A53 and Cortex A57), thus all CPUs need to be enumerated. If the kernel does not have valid information to populate these entries with, an empty string is returned to userspace. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Signed-off-by: Steve Capper [ Return error for access to !present CPU registers, ABI documentation updates, Protection from hotplug ] Signed-off-by: Suzuki K. Poulose --- Changes since V4: - Update the comment about exporting 64bit value Changes since V3: - Disable cpu hotplug while we initialise - Added a comment to explain why expose 64bit value - Update Document/ABI/testing/sysfs-devices-system-cpu Changes since V2: - Fix errno for failures (Spotted-by: Russell King) - Roll back, if we encounter a missing cpu device - Return error for access to registers of CPUs not present. --- Documentation/ABI/testing/sysfs-devices-system-cpu | 13 ++++ arch/arm64/include/asm/cpu.h | 1 + arch/arm64/kernel/cpuinfo.c | 84 ++++++++++++++++++++++ 3 files changed, 98 insertions(+) -- 1.9.1 diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu index 1650133..8c4607d 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -340,3 +340,16 @@ Description: POWERNV CPUFreq driver's frequency throttle stats directory and 'policyX/throttle_stats' directory and all the attributes are same as the /sys/devices/system/cpu/cpuX/cpufreq/throttle_stats directory and attributes which give the frequency throttle information of the chip. + +What: /sys/devices/system/cpu/cpuX/identification/ + /sys/devices/system/cpu/cpuX/identification/midr + /sys/devices/system/cpu/cpuX/identification/revidr +Date: June 2016 +Contact: Linux ARM Kernel Mailing list + Linux Kernel mailing list +Description: ARM64 CPU identification registers + 'identification' directory exposes the CPU ID registers for + identifying model and revision of the CPU. + - midr : This file gives contents of Main ID Register (MIDR_EL1). + - revidr : This file gives contents of the Revision ID register + (REVIDR_EL1). diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index 13a6103..116a382 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -29,6 +29,7 @@ struct cpuinfo_arm64 { u32 reg_cntfrq; u32 reg_dczid; u32 reg_midr; + u32 reg_revidr; u64 reg_id_aa64dfr0; u64 reg_id_aa64dfr1; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index c173d32..dd3168c 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -212,6 +212,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_ctr = read_cpuid_cachetype(); info->reg_dczid = read_cpuid(DCZID_EL0); info->reg_midr = read_cpuid_id(); + info->reg_revidr = read_cpuid(REVIDR_EL1); info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); @@ -264,3 +265,86 @@ void __init cpuinfo_store_boot_cpu(void) boot_cpu_data = *info; init_cpu_features(&boot_cpu_data); } + +/* + * The ARM ARM uses the phrase "32-bit register" to describe a register + * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however + * no statement is made as to whether the upper 32 bits will or will not + * be made use of in future, and between ARM DDI 0487A.c and ARM DDI + * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. + * + * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit + * registers, we expose them both as 64 bit values to cater for possible + * future expansion without an ABI break. + */ +#define CPUINFO_ATTR_RO(_name) \ + static ssize_t show_##_name (struct device *dev, \ + struct device_attribute *attr, char *buf) \ + { \ + struct cpuinfo_arm64 *info = &per_cpu(cpu_data, dev->id); \ + if (!cpu_present(dev->id)) \ + return -ENODEV; \ + \ + if (info->reg_midr) \ + return sprintf(buf, "0x%016x\n", info->reg_##_name); \ + else \ + return 0; \ + } \ + static DEVICE_ATTR(_name, 0444, show_##_name, NULL) + +CPUINFO_ATTR_RO(midr); +CPUINFO_ATTR_RO(revidr); + +static struct attribute *cpuregs_attrs[] = { + &dev_attr_midr.attr, + &dev_attr_revidr.attr, + NULL +}; + +static struct attribute_group cpuregs_attr_group = { + .attrs = cpuregs_attrs, + .name = "identification" +}; + +static int __init cpuinfo_regs_init(void) +{ + int cpu, finalcpu, ret; + struct device *dev; + + cpu_hotplug_disable(); + + for_each_present_cpu(cpu) { + dev = get_cpu_device(cpu); + + if (!dev) { + ret = -ENODEV; + break; + } + + ret = sysfs_create_group(&dev->kobj, &cpuregs_attr_group); + if (ret) + break; + } + + if (!ret) + goto out; + /* + * We were unable to put down sysfs groups for all the CPUs, revert + * all the groups we have placed down s.t. none are visible. + * Otherwise we could give a misleading picture of what's present. + */ + finalcpu = cpu; + for_each_present_cpu(cpu) { + if (cpu == finalcpu) + break; + dev = get_cpu_device(cpu); + if (dev) + sysfs_remove_group(&dev->kobj, &cpuregs_attr_group); + } + +out: + cpu_hotplug_enable(); + return ret; +} + +device_initcall(cpuinfo_regs_init);