From patchwork Tue Jun 21 18:41:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 70591 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp2164480qgy; Tue, 21 Jun 2016 11:41:38 -0700 (PDT) X-Received: by 10.36.253.3 with SMTP id m3mr8173990ith.52.1466534498429; Tue, 21 Jun 2016 11:41:38 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x8si41548243pfj.230.2016.06.21.11.41.37; Tue, 21 Jun 2016 11:41:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753169AbcFUSld (ORCPT + 30 others); Tue, 21 Jun 2016 14:41:33 -0400 Received: from mail-it0-f49.google.com ([209.85.214.49]:35884 "EHLO mail-it0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752372AbcFUSla (ORCPT ); Tue, 21 Jun 2016 14:41:30 -0400 Received: by mail-it0-f49.google.com with SMTP id a5so81044702ita.1 for ; Tue, 21 Jun 2016 11:41:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=rEVi+XcLE15tzGoW+Sa3VvMa8EU0tqfTbAiuyRRWyYU=; b=RytCxM5qLuN51il4f0vT0m/8LzifmyBNKp2IrVRdkZAZRHIbhA/9XtED9nOl99r+J9 lzaf6fTicmceppC+9p55CbwxHZ1n7bYnOb5eAQUjKlehUxmeR8ruUkB0GEmO/YJ3Dzh5 L7gXY8X1+zTij9x3C8HBEYOiIx2S1FGbER74k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=rEVi+XcLE15tzGoW+Sa3VvMa8EU0tqfTbAiuyRRWyYU=; b=dRaVg3KeNmxd+cfAeP574EvxzweTc21T6PV2CX119vbbnNzq7PoCaZfBd8TPmkW3BT gGQUji882gXq6Tk9MxtJ6N29DCj9COZa6n/OwXMONHZ1JUv/oiZh1lydfSdYyQ90PizZ zJ3hPeAcMLjbyaciMPHXvaAfLs6EiWXObgepLn6i2jNGwzm3A+wYO926bzOpZGwIZtO5 rbkCOA8utloEWmlPG0JyeCUBhjymYoNlesTBaCLjsiGFBsy5fwUJcxgpcR72QliPmdb/ f2zgBn9PHWdjqD8feY+soTS4VBJHmGfSBYx28BQcqso9eMMGgMBWO3BxWrxF4vOrNwDK +GEw== X-Gm-Message-State: ALyK8tJ2QVIys36ao7+nai6Fl1JIW2sUxrUC2vCX20o/9f3Rfvyn5vL9aO5ptiWpYSF4jzQF X-Received: by 10.36.104.206 with SMTP id v197mr8448499itb.54.1466534489407; Tue, 21 Jun 2016 11:41:29 -0700 (PDT) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id d15sm1922419itb.12.2016.06.21.11.41.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 Jun 2016 11:41:28 -0700 (PDT) From: Mathieu Poirier To: robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sudeep.holla@arm.com, suzuki.poulose@arm.com, olof@lixom.net Subject: [PATCH] coresight: document binding acronyms Date: Tue, 21 Jun 2016 12:41:26 -0600 Message-Id: <1466534486-22422-1-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It can be hard for people not familiar with the CoreSight IP blocks to make sense of the acronyms found in the current bindings. As such this patch expands each acronym in the hope of providing a better description of the IP block they represent. Signed-off-by: Mathieu Poirier --- .../devicetree/bindings/arm/coresight.txt | 32 ++++++++++++++++------ 1 file changed, 24 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 93147c0c8a0e..c73a7f773998 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -12,14 +12,30 @@ its hardware characteristcs. * compatible: These have to be supplemented with "arm,primecell" as drivers are using the AMBA bus interface. Possible values include: - - "arm,coresight-etb10", "arm,primecell"; - - "arm,coresight-tpiu", "arm,primecell"; - - "arm,coresight-tmc", "arm,primecell"; - - "arm,coresight-funnel", "arm,primecell"; - - "arm,coresight-etm3x", "arm,primecell"; - - "arm,coresight-etm4x", "arm,primecell"; - - "qcom,coresight-replicator1x", "arm,primecell"; - - "arm,coresight-stm", "arm,primecell"; [1] + - Embedded Trace Buffer (version 1.0): + "arm,coresight-etb10", "arm,primecell"; + + - Trace Port Interface Unit: + "arm,coresight-tpiu", "arm,primecell"; + + - Trace Memory Controller (ETB, ETF, ETR): + "arm,coresight-tmc", "arm,primecell"; + + - Trace Funnel: + "arm,coresight-funnel", "arm,primecell"; + + - Embedded Trace Macrocell (version 3.x) and + Program Flow Trace Macrocell: + "arm,coresight-etm3x", "arm,primecell"; + + - Embedded Trace Macrocell (version 4.x): + "arm,coresight-etm4x", "arm,primecell"; + + - Qualcomm Configurable Replicator (version 1.x): + "qcom,coresight-replicator1x", "arm,primecell"; + + - System Trace Macrocell: + "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component.