From patchwork Fri Jun 24 15:09:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 70828 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp997865qgy; Fri, 24 Jun 2016 08:09:30 -0700 (PDT) X-Received: by 10.98.107.129 with SMTP id g123mr8237398pfc.62.1466780970143; Fri, 24 Jun 2016 08:09:30 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w9si7254609paz.164.2016.06.24.08.09.29; Fri, 24 Jun 2016 08:09:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751573AbcFXPJ2 (ORCPT + 30 others); Fri, 24 Jun 2016 11:09:28 -0400 Received: from mail-io0-f181.google.com ([209.85.223.181]:33043 "EHLO mail-io0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751183AbcFXPJ0 (ORCPT ); Fri, 24 Jun 2016 11:09:26 -0400 Received: by mail-io0-f181.google.com with SMTP id t74so101765421ioi.0 for ; Fri, 24 Jun 2016 08:09:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=/5yFwCIgmDu1SLYqnLhon0wXSPhWrCSO7soDPBDcCTo=; b=NhxP++I08q5R3+6kvZSf2xK9+kNeNxCKqBs8+3b23PXIqFglJQOACsm+/cbm5K6x0X 54vCxTWzIfEhpH+Aa5twdix2LDYVvopRoLkLM1Bd6bCyX591oPTf1qwKbeYhP9Wtcof3 5+U3QsRWRIxYLuXnkuTgFDELwPaLGPUNlKyKs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=/5yFwCIgmDu1SLYqnLhon0wXSPhWrCSO7soDPBDcCTo=; b=DXHzvdOW+VRiUa8weiOAQaoFpFubAOVZvsPI7yM5sLtgCWz3FlcsZuRZrtLJ7T3SB7 aXxq9eDLSLrWfU+xBQlLnI+OMdiC9DgSXSksaH1AWlcoOp9Mk/HGO774JRsn77wNjVOR LjUnoXZIEfNry8Wl/kWcIhhYc1S0DCMCYJPHw3NzerDI7ySLseXzq/YciEQe9vqxLLfZ Qci5YmIrCL76/ZfbNNlBzKEVI8fNUA9moHPti4iMDz3VOjpsxvg+XXNMsNj/fSroVqg9 4GkPSTqD6JVpPAwDYaVnzNuIg2RQ+lKSM6z1PmPsW0KHzbs6AU5zWIw+tXv0dcazVuEB BzZA== X-Gm-Message-State: ALyK8tKhfceyCWcqjdF2PhG7zICjm31alI2N2IPsi1QtJ4a6k6nTW+7IcfBG4DWLcV63aUGd X-Received: by 10.107.163.7 with SMTP id m7mr6787847ioe.105.1466780965870; Fri, 24 Jun 2016 08:09:25 -0700 (PDT) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id q128sm3066927iod.30.2016.06.24.08.09.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Jun 2016 08:09:25 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com Cc: linux-kernel@vger.kernel.org Subject: [PATCH V2] coresight: add PM runtime calls to coresight_simple_func() Date: Fri, 24 Jun 2016 09:09:23 -0600 Message-Id: <1466780963-21396-1-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It is mandatory to enable a coresight block's power domain before trying to access management registers. Otherwise the transaction simply stalls, leading to a system hang. Signed-off-by: Mathieu Poirier --- Change from V1: - Fix erroneous return point in the macro. drivers/hwtracing/coresight/coresight-priv.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.7.4 Reviewed-by: Sudeep Holla diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index ad975c58080d..decfd52b5dc3 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -16,6 +16,7 @@ #include #include #include +#include /* * Coresight management registers (0xf00-0xfcc) @@ -42,8 +43,11 @@ static ssize_t name##_show(struct device *_dev, \ struct device_attribute *attr, char *buf) \ { \ type *drvdata = dev_get_drvdata(_dev->parent); \ - return scnprintf(buf, PAGE_SIZE, "0x%x\n", \ - readl_relaxed(drvdata->base + offset)); \ + u32 val; \ + pm_runtime_get_sync(_dev->parent); \ + val = readl_relaxed(drvdata->base + offset); \ + pm_runtime_put_sync(_dev->parent); \ + return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); \ } \ static DEVICE_ATTR_RO(name)