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c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=QiRru1hggv1EzAPvAxur7MoqQyAiUFvFwSEtMTS1MGs=; b=4mkCtpRCfpbRi1qV+nhR97aN6ljIQEDKWyyLjltNIood++IpvL4x4Clbsx/kS2+oot+X0p8Ce6bvcgAe83jJzrQICn/A8Q6xmUpoc93MuOOoFodNf1YzolTuhLkPy8m1sGb7yGmqUsqZvZafELwcNrMo0RK77F8vooQCcV+xErI= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; Received: from localhost.localdomain (114.109.128.54) by SN1PR12MB0445.namprd12.prod.outlook.com (10.162.105.139) with Microsoft SMTP Server (TLS) id 15.1.534.14; Wed, 13 Jul 2016 13:21:33 +0000 From: Suravee Suthikulpanit To: , , , CC: , , , Suravee Suthikulpanit Subject: [PART2 PATCH v4 08/11] iommu/amd: Implements irq_set_vcpu_affinity() hook to setup vapic mode for pass-through devices Date: Wed, 13 Jul 2016 08:20:29 -0500 Message-ID: <1468416032-7692-9-git-send-email-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1468416032-7692-1-git-send-email-suravee.suthikulpanit@amd.com> References: <1468416032-7692-1-git-send-email-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [114.109.128.54] X-ClientProxiedBy: SIXPR04CA0024.apcprd04.prod.outlook.com (10.162.171.14) To SN1PR12MB0445.namprd12.prod.outlook.com (10.162.105.139) X-MS-Office365-Filtering-Correlation-Id: 20ac9c6f-9f10-4445-8b60-08d3ab209d69 X-Microsoft-Exchange-Diagnostics: 1; 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In case requirements for vapic mode are not met, it falls back to set up the IRTE in legacy mode. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd_iommu.c | 68 ++++++++++++++++++++++++++++++++++++++++++++--- include/linux/amd-iommu.h | 6 +++++ 2 files changed, 70 insertions(+), 4 deletions(-) -- 1.9.1 diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index 4a337dc..1b81af8 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -3907,7 +3907,8 @@ out: return index; } -static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte) +static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte, + struct amd_ir_data *data) { struct irq_remap_table *table; struct amd_iommu *iommu; @@ -3933,6 +3934,8 @@ static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte) entry->hi.fields.ga_root_ptr = tmp.hi.fields.ga_root_ptr; entry->lo.val = irte->lo.val; entry->lo.fields_remap.valid = 1; + if (data) + data->ref = entry; spin_unlock_irqrestore(&table->lock, flags); @@ -4031,7 +4034,7 @@ static void irte_ga_activate(void *entry, u16 devid, u16 index) struct irte_ga *irte = (struct irte_ga *) entry; irte->lo.fields_remap.valid = 1; - modify_irte_ga(devid, index, irte); + modify_irte_ga(devid, index, irte, NULL); } static void irte_deactivate(void *entry, u16 devid, u16 index) @@ -4047,7 +4050,7 @@ static void irte_ga_deactivate(void *entry, u16 devid, u16 index) struct irte_ga *irte = (struct irte_ga *) entry; irte->lo.fields_remap.valid = 0; - modify_irte_ga(devid, index, irte); + modify_irte_ga(devid, index, irte, NULL); } static void irte_set_affinity(void *entry, u16 devid, u16 index, @@ -4068,7 +4071,7 @@ static void irte_ga_set_affinity(void *entry, u16 devid, u16 index, irte->hi.fields.vector = vector; irte->lo.fields_remap.destination = dest_apicid; irte->lo.fields_remap.guest_mode = 0; - modify_irte_ga(devid, index, irte); + modify_irte_ga(devid, index, irte, NULL); } #define IRTE_ALLOCATED (~1U) @@ -4403,6 +4406,62 @@ static struct irq_domain_ops amd_ir_domain_ops = { .deactivate = irq_remapping_deactivate, }; +static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) +{ + unsigned long flags; + struct amd_iommu *iommu; + struct amd_iommu_pi_data *pi_data = vcpu_info; + struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; + struct amd_ir_data *ir_data = data->chip_data; + struct irte_ga *irte = (struct irte_ga *) ir_data->entry; + struct irq_2_irte *irte_info = &ir_data->irq_2_irte; + + /* Note: + * SVM tries to set up for VAPIC mode, but we are in + * legacy mode. So, we force legacy mode instead. + */ + if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { + pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n", + __func__); + vcpu_pi_info = NULL; + } + + iommu = amd_iommu_rlookup_table[irte_info->devid]; + if (iommu == NULL) + return -EINVAL; + + spin_lock_irqsave(&iommu->gatag_ir_hash_lock, flags); + + if (vcpu_pi_info) { + /* Setting */ + irte->hi.fields.vector = vcpu_pi_info->vector; + irte->lo.fields_vapic.guest_mode = 1; + irte->lo.fields_vapic.ga_tag = + AMD_IOMMU_GATAG(pi_data->vm_id, pi_data->vcpu_id); + + if (!hash_hashed(&ir_data->hnode)) + hash_add(iommu->gatag_ir_hash, &ir_data->hnode, + (u16)(irte->lo.fields_vapic.ga_tag)); + } else { + /* Un-Setting */ + struct irq_cfg *cfg = irqd_cfg(data); + + irte->hi.val = 0; + irte->lo.val = 0; + irte->hi.fields.vector = cfg->vector; + irte->lo.fields_remap.guest_mode = 0; + irte->lo.fields_remap.destination = cfg->dest_apicid; + irte->lo.fields_remap.int_type = apic->irq_delivery_mode; + irte->lo.fields_remap.dm = apic->irq_dest_mode; + + hash_del(&ir_data->hnode); + } + + spin_unlock_irqrestore(&iommu->gatag_ir_hash_lock, flags); + + return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data); +} + static int amd_ir_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) { @@ -4447,6 +4506,7 @@ static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) static struct irq_chip amd_ir_chip = { .irq_ack = ir_ack_apic_edge, .irq_set_affinity = amd_ir_set_affinity, + .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, .irq_compose_msi_msg = ir_compose_msi_msg, }; diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index a6fc022..0928c26 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -22,6 +22,12 @@ #include +struct amd_iommu_pi_data { + u32 vcpu_id; + u32 vm_id; + struct vcpu_data *vcpu_data; +}; + #ifdef CONFIG_AMD_IOMMU struct task_struct;