From patchwork Tue Aug 23 18:52:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Suthikulpanit, Suravee" X-Patchwork-Id: 74514 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp2247051qga; Tue, 23 Aug 2016 11:57:57 -0700 (PDT) X-Received: by 10.98.17.83 with SMTP id z80mr56598177pfi.38.1471978677217; Tue, 23 Aug 2016 11:57:57 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u17si5076217pal.232.2016.08.23.11.57.56; Tue, 23 Aug 2016 11:57:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@amdcloud.onmicrosoft.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754601AbcHWS5n (ORCPT + 27 others); Tue, 23 Aug 2016 14:57:43 -0400 Received: from mail-cys01nam02on0075.outbound.protection.outlook.com ([104.47.37.75]:52743 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753002AbcHWS5f (ORCPT ); Tue, 23 Aug 2016 14:57:35 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=uWQBpnqZ+dyywcovEods3ZfEfzvTBlbX+EXdcEuwrzA=; b=EWcZALOJ2CxXcUIoXaUK/uE5jE6q2exmE5ZD1q/LvaXOpA72i9IO11qJ0GQwGG6wn6or8V1KT4MAEx7qtlxxCGDqhwmRJzhm1trwXPXFO0GjQFQTjEZGe97E83SLLurxJWhS6mo+XRekSZyYRw853cZ30GW57gnA0FAJykpa2Aw= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; Received: from localhost.localdomain (114.109.128.54) by DM5PR12MB1452.namprd12.prod.outlook.com (10.172.38.141) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA_P384) id 15.1.557.21; Tue, 23 Aug 2016 18:53:32 +0000 From: Suravee Suthikulpanit To: , , , CC: , , , Suravee Suthikulpanit Subject: [PART2 PATCH v7 08/12] iommu/amd: Implements irq_set_vcpu_affinity() hook to setup vapic mode for pass-through devices Date: Tue, 23 Aug 2016 13:52:39 -0500 Message-ID: <1471978363-13756-9-git-send-email-Suravee.Suthikulpanit@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1471978363-13756-1-git-send-email-Suravee.Suthikulpanit@amd.com> References: <1471978363-13756-1-git-send-email-Suravee.Suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [114.109.128.54] X-ClientProxiedBy: KL1PR02CA0053.apcprd02.prod.outlook.com (10.167.54.21) To DM5PR12MB1452.namprd12.prod.outlook.com (10.172.38.141) X-MS-Office365-Filtering-Correlation-Id: 52a92b70-df9e-43e6-1fa1-08d3cb86c996 X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1452; 2:gPxOFN9AtBr/rYOLzQQJs54oTs3SUWjUM+lVhgfJxTK0aG/Ht0aCgGhvCPzQEsAJJqKqWWGxN1zGsY/6SeCqwjFh8tOBSmyhDNevZ82x16sCkVyHvWByxiSEvQBsdrt2V/M3Psm8e9RdZER7N+L9gaBB8hXSoyLw5stxsrYgYOjAXS/HFfjw2aijoqBzdWLp; 3:TBINh1yEyOT9wgMZf3LYWOrSA1gkqsDYy3dcQKZiYIzD4WqBPz3AB4MwvtL/2BjmkI0Xpui+fUm+g69skYJ4jzbaCOsZzv2voywx2AQJcI3iA5Kf3nY/yXspEYFA7c1U; 25:FJ0fgfKjcUqitSjbPrCCnL/7aBRuB50W51CZt5rVml3zRC3N8tMrX65Nrj04Gq86gLsosyjE0m3E0gfRbUzrg0ahicjCokXszC+/19KKxNEjNAXDdYelQoduIBA3upRB7A6dLbswSVHrEcht4sH69EwP3WRcN8YG75N7aByJNVNQW94ufx64bqpu2rNf7biuabNRdqQfr21cL4J37yK8bjUcEaTlOrhjbbNt2TiZ7bFBiOFmYnRBlcy7Fbh3B9v7wi+3lo01O94peKhXhMVrTrs4L8VbF7yVLGIdBV+63bCmDzM6KXDNfnQZQh+4AzP04WuUGmba0QZC7TqaqCq7i3Wl0JddShUDbTToDeMhHxplV5x1aKzNeH7/bW64hd3eY29NEh2xv3PCe6vUg14QfVOFPjuGvILIH45/7PG2E9Q= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DM5PR12MB1452; X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1452; 31:KSbEKnGM9Yiu9YH9hgKrY3Fvf0csHejkn/t/r3up0mOFGbZ4s5tqTwdm+NCbrw+iXUhR6hHi9u7qqWfInDlgZq5lGIbS11nB6oe5BIsxsnbL7MQJc9gMHam+3pDSK6rtsTbi+vsLKrDCNniFjsu9YzqXAIh/PsLZIpoROK87nRU8jd0p/UrUKz0aPOH2bXWD/2K4P6yDtVmpRfxUVyrZrj9Pxn3ms53syCB4X4eH/C8=; 20:DR2o5pyxg7fXRvea3zWViyqY144e6tY2O0R/M7XEzVyTWKXzfqFlBs5m3a5runcbIPP1rgRpb2FH5rm3wQ/C0vvxw93JwyOuzeiaWG9T/leFYJtuiiIcdEtwrlHspVn7qPuwsoD4CJRRRXA5vtWH7KPKb/DjWDl9UUjUvH5HVt7BIZVPhUot8bnKDDsIleliEhYyoUWNU3jIYBm+l+LtlxnBu4iyIeawHRdQ9FvgNU0Lm2BikJgb1ipL5rQmqGeS4GaPndCLsVzxpU8DLloJGUfnFCrNYxUEPWeCpUx2iVgnHe9YTEPK5vXuTZNT6jzcJGc7FJUyOvtwkxeHsux9oZ+vnVMkJc6gX1L21NYofyu37TW5AyZ9miEmmjBowE898A2WJEt+OEpUj7arPTQLBRwP8K2sgTGM9RESTLp9ZmsXEhgRu6TNKOpw2eS8CaRzrj166B96nVke678m+JA5d2JLtisFX8qQfurqeccdlYvho3gWRalc/QlhOziA4AMy X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(767451399110); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040176)(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046)(6055026); SRVR:DM5PR12MB1452; BCL:0; PCL:0; RULEID:; SRVR:DM5PR12MB1452; X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1452; 4:hQ00BcAzsmp/M11SqwfEaa48Ogy2XZ3sgp4IRtK2S4ttZHoxk69GYV3MPpPMJrz4snMhcny3BJrPpzVmnF1JRbKhfvtlhSdnZ6cm24SsrpE2W+OTFeObrcECH+fYKCDFlbRwN9B7v/fl9n/2mMh0ei/8O13K9di40IF1MZ3qwFtbSCwgP72ZsqXhMAU1fXd8DsYMpv2GeMtfx3pqWB+oOBH2ccntLJTHgEd2IqMcA20xKs9BKW6ODIXsuNDci+2uWWOZrX62qTQG+UBY6ANtR/7BRHT3NAgPyZSXaO+b3zATAELrCpvZqSIuOYfZcULQzH4ciRIE3kcPIwqEYlt5SHQJNZiXc/9t+KtLiVMglQ0Fwgoa2UIpBUVXTI5T4yJOdMtTcUdL7Do22aLu9QhT+Q5mJHtd7CDq4jHaAVMAEY/9aAeXuL0zHSh4ZhnlPNrW X-Forefront-PRVS: 004395A01C X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4630300001)(6069001)(6009001)(7916002)(199003)(189002)(42186005)(76176999)(101416001)(48376002)(50466002)(77096005)(5660300001)(575784001)(92566002)(105586002)(5003940100001)(36756003)(86362001)(106356001)(66066001)(50986999)(5001770100001)(19580395003)(19580405001)(50226002)(97736004)(189998001)(229853001)(3846002)(2950100001)(47776003)(8676002)(7736002)(6116002)(586003)(81156014)(68736007)(4326007)(2201001)(81166006)(305945005)(7846002)(2906002); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1452; H:localhost.localdomain; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM5PR12MB1452; 23:V9sSKj8rR1oyF3yKDIEFU9BfZlzR2jp3OpTDp02k3?= =?us-ascii?Q?E8twgkjQW0jVVNzdfEt/rz27BgW46LcltYrmtDRSK2b+DINnPKbRjj4eVKHr?= =?us-ascii?Q?6D5+Gq58j+8BIrzz+oGO37hDp8gYMLoML50POVAnyD2ekGvNZvg5ihhzAo4w?= =?us-ascii?Q?kuhCcKfaEViPhDnrFB/MCCCa5gGLeaiuEpRbl94bEWRcTjnIUvgw+M2umbYw?= =?us-ascii?Q?IZks96CTAAziyS8oMBMHXlJFoiIu59u4EKFZjDidORzW/xg+R90pVKlsKcHg?= =?us-ascii?Q?oEgD+NAY8iIMrtULn7rDIjL1M/O8x1F5T5srg5QrvyGHDF/+Oj64pMwi80nN?= =?us-ascii?Q?H0VR2hH3xFNB3CsdKj43bQwTqTVc6Vv5q2C+BwvrKC7xNuR7Karqb8zIQzyG?= =?us-ascii?Q?KRQJfRmzLjY9ha/BjhMYlf8N9rRpI10mRIkY8o8K1bgv/FL8saD6KBOBFKbI?= =?us-ascii?Q?B0RqHDlgrG3D0gImHbDmdXT8kZV6cNkUl2sFFsPU/VbpI/1ZJb5opa9pdZNY?= =?us-ascii?Q?0I/mpFFwevw16WOD2EfFyBX5zbLaozNI5OurH0a0Gl6ZdTRWvh8TDuiQCl0k?= =?us-ascii?Q?A8d0bkfiPJJMuG/hhOyLSzw/6rv/op0WaTwe+It39XmWP/2qe0k/BiiuEHSg?= =?us-ascii?Q?N1Zaj6jSLafpaVQeFe4VX5y1axeRSNRrRbIgi+1K7CXj6yY3tJzcypjX0YFY?= =?us-ascii?Q?sjrIn0WXGN3DuDU9ilqD9FohAnRejboK/6LTsvEYEhMQjzNB45TB7UjiNX8k?= =?us-ascii?Q?QpvYdGyha21gYJuevNQE6sHed3VHSajoeUBanJNB0G4uSv1ShtihgP4xbkPQ?= =?us-ascii?Q?IFiy4Q4yQUlks/Cb7nPbBJyuVodsmjudHDam39gtrO3/rvpDf8WHwcl5Vx6d?= =?us-ascii?Q?6m0rzCdIG4UZTjvejHNEQvf4nPuYHjv7LZACwGSx7hnCLKj/5b9amtRefGch?= =?us-ascii?Q?bO5B/mI/Cdbi6iLyeZtPHHqZwT/0ycmuOqrka16wgrpWfWt95/EUjVsrhUD5?= =?us-ascii?Q?zAAk9cgbmY1LaREQeU+P6Jp6l2MrMY7xvOMe/oxwVmQlvF+vqgrOEWWxzFmg?= =?us-ascii?Q?O8bQiZEoTRQ0ADzJRR4LEFmosEkZbtZ4zbdvTTH9AJ+q3WfhpxoBbYtiL741?= =?us-ascii?Q?NEDCndKzDI=3D?= X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1452; 6:eARfhmVaMagMQzaTmYBvqYA3+0aXMlaBZfkN0v8NfFvqkrnlDdR577w9Yd8IZDuGAcd/g0sbi3+GwWbQjSBsyqNTpRJ1uMXxmeBWzjw1H3ocx9TIiPLC5kN1TisSmzTHvbb8HB1F4OtS+Z3UVC6caUZx0ByI/17jfekM51cqKHoYE1dsVZmtwTIYzmXAiVc8ImTLYK8O+UGhF5RFfugC0LGVA3kTLcpbnAs4M/4mBnU+PC+vga7ApcA8QbMnfQe2/FWrqc4oXLcnVVT2hNCZF1elEgVpMouftb3H5D6FnuAqQ0LP7FHfRF0Uat8dxHj5d3U9xEW/PNi9Jy3K6G4SlA==; 5:4hpffh9TjteJKEtMDT60SuuJGmrMR+5KM0oJwzuy22spx0XUTUXXJLxo+EjEg4Y3m7ca5V0RY6e94p50Oq1vR82jyf1u+n4Fej8hRunBVZXtdsjw/aIP/NYGx7EEW+l306J8LZmmpw2BH0fFHDmcmw==; 24:A2RwIt6n2xOBPClqFhwX/yJX7RdiEAQM9YQ5CxcpA/V8q5BT8u7o/NuCHnf4UnlipxnviqRhIvljADpvsTs3QTutWWLHJCrkrOsY2FlZ7DE=; 7:e/CMoA+f2VQidqBQwxSSmZVJgE5taKpJRdl4J9oQHGbjShpXM1Kyw2RmZ5LefdJImSWCWW3MfO1pg2eikyL41+FivppnH43+FTBMQnaffPwZgrSMBsc+bq/9/qk55cQ2cQzp41xMrXK4rLloxRqb0Td4wQ1BxZXaCk90UaUmpgX1lzQg8GsPvbFMv7MqgwKYdmuGaGFWp27AJbnjMZtdMKMixRGZ8RGdTtjJY9ihJrhD29ZHNr+tcaSlx/L9aTIt SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1452; 20:oIQg2JfbCJFuj2QKv6eLQse7CpnS4YQN/MDBcr6ijW0nGNqBpMn/an3z6DAqQsSYEpTjDfRTHBj5uK+spFCxVdR80h3AU9UYrgSYZuctnukfuxU3TexVZ3tjzfsdpu04mRw6F/fFe49XMxywWJnnXJyUjJjeyPIS0B4fMbQDVUsbsBREj0xioUKhbGwDQitlRdUtfXukNm7XJ6RRrt7u13hGy8RvGTY4rH2nLBBV9JyrXDlpFsuG3QIbwDzlJxQn X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2016 18:53:32.8332 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1452 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suravee Suthikulpanit This patch implements irq_set_vcpu_affinity() function to set up interrupt remapping table entry with vapic mode for pass-through devices. In case requirements for vapic mode are not met, it falls back to set up the IRTE in legacy mode. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd_iommu.c | 68 ++++++++++++++++++++++++++++++++++++++--- drivers/iommu/amd_iommu_types.h | 1 + include/linux/amd-iommu.h | 14 +++++++++ 3 files changed, 79 insertions(+), 4 deletions(-) -- 1.9.1 diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index 9f91480..7aa0c08 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -3900,7 +3900,8 @@ out: return index; } -static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte) +static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte, + struct amd_ir_data *data) { struct irq_remap_table *table; struct amd_iommu *iommu; @@ -3923,6 +3924,8 @@ static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte) entry->hi.val = irte->hi.val; entry->lo.val = irte->lo.val; entry->lo.fields_remap.valid = 1; + if (data) + data->ref = entry; spin_unlock_irqrestore(&table->lock, flags); @@ -4021,7 +4024,7 @@ static void irte_ga_activate(void *entry, u16 devid, u16 index) struct irte_ga *irte = (struct irte_ga *) entry; irte->lo.fields_remap.valid = 1; - modify_irte_ga(devid, index, irte); + modify_irte_ga(devid, index, irte, NULL); } static void irte_deactivate(void *entry, u16 devid, u16 index) @@ -4037,7 +4040,7 @@ static void irte_ga_deactivate(void *entry, u16 devid, u16 index) struct irte_ga *irte = (struct irte_ga *) entry; irte->lo.fields_remap.valid = 0; - modify_irte_ga(devid, index, irte); + modify_irte_ga(devid, index, irte, NULL); } static void irte_set_affinity(void *entry, u16 devid, u16 index, @@ -4058,7 +4061,7 @@ static void irte_ga_set_affinity(void *entry, u16 devid, u16 index, irte->hi.fields.vector = vector; irte->lo.fields_remap.destination = dest_apicid; irte->lo.fields_remap.guest_mode = 0; - modify_irte_ga(devid, index, irte); + modify_irte_ga(devid, index, irte, NULL); } #define IRTE_ALLOCATED (~1U) @@ -4393,6 +4396,62 @@ static struct irq_domain_ops amd_ir_domain_ops = { .deactivate = irq_remapping_deactivate, }; +static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) +{ + struct amd_iommu *iommu; + struct amd_iommu_pi_data *pi_data = vcpu_info; + struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; + struct amd_ir_data *ir_data = data->chip_data; + struct irte_ga *irte = (struct irte_ga *) ir_data->entry; + struct irq_2_irte *irte_info = &ir_data->irq_2_irte; + + pi_data->ir_data = ir_data; + + /* Note: + * SVM tries to set up for VAPIC mode, but we are in + * legacy mode. So, we force legacy mode instead. + */ + if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { + pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n", + __func__); + pi_data->is_guest_mode = false; + } + + iommu = amd_iommu_rlookup_table[irte_info->devid]; + if (iommu == NULL) + return -EINVAL; + + pi_data->prev_ga_tag = ir_data->cached_ga_tag; + if (pi_data->is_guest_mode) { + /* Setting */ + irte->hi.fields.ga_root_ptr = (pi_data->base >> 12); + irte->hi.fields.vector = vcpu_pi_info->vector; + irte->lo.fields_vapic.guest_mode = 1; + irte->lo.fields_vapic.ga_tag = pi_data->ga_tag; + + ir_data->cached_ga_tag = pi_data->ga_tag; + } else { + /* Un-Setting */ + struct irq_cfg *cfg = irqd_cfg(data); + + irte->hi.val = 0; + irte->lo.val = 0; + irte->hi.fields.vector = cfg->vector; + irte->lo.fields_remap.guest_mode = 0; + irte->lo.fields_remap.destination = cfg->dest_apicid; + irte->lo.fields_remap.int_type = apic->irq_delivery_mode; + irte->lo.fields_remap.dm = apic->irq_dest_mode; + + /* + * This communicates the ga_tag back to the caller + * so that it can do all the necessary clean up. + */ + ir_data->cached_ga_tag = 0; + } + + return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data); +} + static int amd_ir_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) { @@ -4437,6 +4496,7 @@ static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) static struct irq_chip amd_ir_chip = { .irq_ack = ir_ack_apic_edge, .irq_set_affinity = amd_ir_set_affinity, + .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, .irq_compose_msi_msg = ir_compose_msi_msg, }; diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index 6973952..f10b429 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -808,6 +808,7 @@ struct irq_2_irte { }; struct amd_ir_data { + u32 cached_ga_tag; struct irq_2_irte irq_2_irte; struct msi_msg msi_entry; void *entry; /* Pointer to union irte or struct irte_ga */ diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index d8d48ac..09751d3 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -22,6 +22,20 @@ #include +/* + * This is mainly used to communicate information back-and-forth + * between SVM and IOMMU for setting up and tearing down posted + * interrupt + */ +struct amd_iommu_pi_data { + u32 ga_tag; + u32 prev_ga_tag; + u64 base; + bool is_guest_mode; + struct vcpu_data *vcpu_data; + void *ir_data; +}; + #ifdef CONFIG_AMD_IOMMU struct task_struct;