From patchwork Mon Sep 19 07:41:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baoyou Xie X-Patchwork-Id: 76511 Delivered-To: patch@linaro.org Received: by 10.140.106.72 with SMTP id d66csp827989qgf; Mon, 19 Sep 2016 00:41:53 -0700 (PDT) X-Received: by 10.66.156.196 with SMTP id wg4mr44899285pab.153.1474270913366; Mon, 19 Sep 2016 00:41:53 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p187si21845082pfg.52.2016.09.19.00.41.53; Mon, 19 Sep 2016 00:41:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936515AbcISHls (ORCPT + 27 others); Mon, 19 Sep 2016 03:41:48 -0400 Received: from mail-pf0-f173.google.com ([209.85.192.173]:36317 "EHLO mail-pf0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964934AbcISHlf (ORCPT ); Mon, 19 Sep 2016 03:41:35 -0400 Received: by mail-pf0-f173.google.com with SMTP id q2so28072741pfj.3 for ; Mon, 19 Sep 2016 00:41:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=Yn+zzQ4E6bTrphAUnAszuZDRFmwzlDvhDbkCmgaMsn4=; b=LsCnil9CJ7rE+tH1JlgW6lZ9P/XKtVsQYSacSvqht1uJmjFejAw2rgrV3Wx0bnvSbS qs0GHqiimCVWF4FSc+L7HtaNnGLjqzMuvUc/lshQsq70Y5qwsw6B4eQmTvETQTTVXDAP z0gwezXUnuu081zblN50ZXRXdWpAD6WwAyebs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Yn+zzQ4E6bTrphAUnAszuZDRFmwzlDvhDbkCmgaMsn4=; b=cKV+Kg4XfxVTRoqvyTek4beChd0vzvxSE7YMiMrt8hgWJtK9k896wEl1lJDiWfFvr/ mrA/475AfxeGLIfy0VuB/8/NW/2EOBDWlQBh7kMX+J0L0wvv9Q1dffS4MvGdLoDOdw4X R6Na1QCD5SNWgle+VWLSYF3tbUA7DFwqXkDiK2+nDV37U4yFX0YexPuLJD2h0WU9oK1O eF4S4fNA9YDc3vWXNySiHQXA0iT5WYAJo45uWsznZhu5U00EGLP3OASLWan8BSLzSBQE 5C9iIELp8cse6Z7BWOaBu220wj+qmQfyFxUG5B5GFmny0GUxKYcgsfBoOyhm6/N9o4pX jjuQ== X-Gm-Message-State: AE9vXwPyNAboBoVltxp30gBNXPytZfZqkWFEV0CQHU8vaVyB77ODy+h/tQwnPESRZaXmgxUI X-Received: by 10.98.53.65 with SMTP id c62mr44692977pfa.66.1474270894546; Mon, 19 Sep 2016 00:41:34 -0700 (PDT) Received: from localhost.localdomain ([104.237.91.244]) by smtp.gmail.com with ESMTPSA id b7sm68939133pfg.87.2016.09.19.00.41.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Sep 2016 00:41:33 -0700 (PDT) From: Baoyou Xie To: alexander.deucher@amd.com, christian.koenig@amd.com, airlied@linux.ie, Rex.Zhu@amd.com, JinHuiEric.Huang@amd.com, Jammy.Zhou@amd.com, eric.yang2@amd.com, vitaly.prosyak@amd.com, tom.stdenis@amd.com, nils.wallmenius@gmail.com, ray.huang@amd.com, Qingqing.Wang@amd.com, sfr@canb.auug.org.au, funfunctor@folklore1984.net, young.yang@amd.com, Monk.Liu@amd.com Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, arnd@arndb.de, baoyou.xie@linaro.org, xie.baoyou@zte.com.cn Subject: [PATCH] drm/amd/powerplay/hwmgr: mark symbols static where possible Date: Mon, 19 Sep 2016 15:41:18 +0800 Message-Id: <1474270878-8817-1-git-send-email-baoyou.xie@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We get a few warnings when building kernel with W=1: drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_hwmgr.c:69:10: warning: no previous prototype for 'cz_get_eclk_level' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/tonga_hwmgr.c:117:27: warning: no previous prototype for 'cast_phw_tonga_power_state' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/tonga_thermal.c:363:5: warning: no previous prototype for 'tf_tonga_thermal_setup_fan_table' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/iceland_hwmgr.c:139:5: warning: no previous prototype for 'iceland_get_memory_type' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/iceland_thermal.c:363:5: warning: no previous prototype for 'tf_iceland_thermal_setup_fan_table' [-Wmissing-prototypes] .... In fact, these functions are only used in the file in which they are declared and don't need a declaration, but can be made static. So this patch marks these functions with 'static'. Signed-off-by: Baoyou Xie --- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 8 +- .../gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c | 92 +++++++------ .../gpu/drm/amd/powerplay/hwmgr/iceland_thermal.c | 9 +- .../amd/powerplay/hwmgr/tonga_clockpowergating.c | 4 +- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 148 +++++++++++---------- .../amd/powerplay/hwmgr/tonga_processpptables.c | 2 +- .../gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c | 8 +- 7 files changed, 147 insertions(+), 124 deletions(-) -- 2.7.4 diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c index 5ecef17..5afb034 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c @@ -66,7 +66,7 @@ static const struct cz_power_state *cast_const_PhwCzPowerState( return (struct cz_power_state *)hw_ps; } -uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr, +static uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr, uint32_t clock, uint32_t msg) { int i = 0; @@ -1225,7 +1225,7 @@ static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) return 0; } -int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) +static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); @@ -1239,7 +1239,7 @@ int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) return 0; } -int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) +static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); struct phm_clock_voltage_dependency_table *table = @@ -1277,7 +1277,7 @@ int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) return 0; } -int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) +static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c index 8a7ada5..547fb36 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c @@ -136,7 +136,7 @@ static int iceland_read_clock_registers(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int iceland_get_memory_type(struct pp_hwmgr *hwmgr) +static int iceland_get_memory_type(struct pp_hwmgr *hwmgr) { iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); uint32_t temp; @@ -162,7 +162,7 @@ int iceland_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int iceland_enable_acpi_power_management(struct pp_hwmgr *hwmgr) +static int iceland_enable_acpi_power_management(struct pp_hwmgr *hwmgr) { PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1); @@ -175,7 +175,7 @@ int iceland_enable_acpi_power_management(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int iceland_get_mc_microcode_version(struct pp_hwmgr *hwmgr) +static int iceland_get_mc_microcode_version(struct pp_hwmgr *hwmgr) { cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); @@ -262,7 +262,7 @@ static void iceland_trim_voltage_table_to_fit_state_table( * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int iceland_enable_voltage_control(struct pp_hwmgr *hwmgr) +static int iceland_enable_voltage_control(struct pp_hwmgr *hwmgr) { /* enable voltage control */ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); @@ -298,7 +298,7 @@ static int iceland_get_svi2_voltage_table(struct pp_hwmgr *hwmgr, * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int iceland_construct_voltage_tables(struct pp_hwmgr *hwmgr) +static int iceland_construct_voltage_tables(struct pp_hwmgr *hwmgr) { iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); int result; @@ -380,12 +380,12 @@ int iceland_construct_voltage_tables(struct pp_hwmgr *hwmgr) /*---------------------------MC----------------------------*/ -uint8_t iceland_get_memory_module_index(struct pp_hwmgr *hwmgr) +static uint8_t iceland_get_memory_module_index(struct pp_hwmgr *hwmgr) { return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); } -bool iceland_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg) +static bool iceland_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg) { bool result = true; @@ -478,7 +478,7 @@ bool iceland_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg) return result; } -int iceland_set_s0_mc_reg_index(phw_iceland_mc_reg_table *table) +static int iceland_set_s0_mc_reg_index(phw_iceland_mc_reg_table *table) { uint32_t i; uint16_t address; @@ -491,7 +491,9 @@ int iceland_set_s0_mc_reg_index(phw_iceland_mc_reg_table *table) return 0; } -int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_iceland_mc_reg_table *ni_table) +static int +iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, + phw_iceland_mc_reg_table *ni_table) { uint8_t i, j; @@ -690,7 +692,8 @@ static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int iceland_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr) +static int +iceland_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr) { iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); @@ -712,7 +715,7 @@ int iceland_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int iceland_enable_display_gap(struct pp_hwmgr *hwmgr) +static int iceland_enable_display_gap(struct pp_hwmgr *hwmgr) { uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); @@ -735,7 +738,7 @@ int iceland_enable_display_gap(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int iceland_program_voting_clients(struct pp_hwmgr *hwmgr) +static int iceland_program_voting_clients(struct pp_hwmgr *hwmgr) { iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); @@ -781,7 +784,7 @@ static int iceland_upload_firmware(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) +static int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) { iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); @@ -873,7 +876,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) * Copy one arb setting to another and then switch the active set. * arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants. */ -int iceland_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, +static int iceland_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, uint32_t arbFreqSrc, uint32_t arbFreqDest) { uint32_t mc_arb_dram_timing; @@ -930,7 +933,7 @@ int iceland_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, * @return always 0 * This function is to be called from the SetPowerState table. */ -int iceland_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr) +static int iceland_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr) { return iceland_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); } @@ -1414,7 +1417,7 @@ int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr) * @return always 0 */ -int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, +static int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, SMU71_Discrete_DpmTable *table) { int result; @@ -1456,7 +1459,7 @@ static uint32_t iceland_get_dpm_level_enable_mask_value( return mask_value; } -int iceland_populate_memory_timing_parameters( +static int iceland_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, @@ -1492,7 +1495,7 @@ int iceland_populate_memory_timing_parameters( * @return always 0 * This function is to be called from the SetPowerState table. */ -int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) +static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) { iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); int result = 0; @@ -2014,7 +2017,8 @@ static int iceland_populate_single_memory_level( * @param mclk the MCLK value to be used in the decision if MVDD should be high or low. * @param voltage the SMC VOLTAGE structure to be populated */ -int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMU71_Discrete_VoltageLevel *voltage) +static int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, + SMU71_Discrete_VoltageLevel *voltage) { const iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); uint32_t i = 0; @@ -2193,7 +2197,7 @@ static int iceland_find_boot_level(struct iceland_single_dpm_table *table, uint3 * @param engine_clock the engine clock to use to populate the structure * @param sclk the SMC SCLK structure to be populated */ -int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr, +static int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) { const iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); @@ -2606,7 +2610,7 @@ static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr) * @param pInput the pointer to input data (PowerState) * @return always 0 */ -int iceland_init_smc_table(struct pp_hwmgr *hwmgr) +static int iceland_init_smc_table(struct pp_hwmgr *hwmgr) { int result; iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); @@ -2791,7 +2795,8 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr) return result; } -int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU71_Discrete_MCRegisters *mc_reg_table) +static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr, + SMU71_Discrete_MCRegisters *mc_reg_table) { const struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); @@ -2815,7 +2820,7 @@ int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU71_Discrete_MCReg } /* convert register values from driver to SMC format */ -void iceland_convert_mc_registers( +static void iceland_convert_mc_registers( const phw_iceland_mc_reg_entry * pEntry, SMU71_Discrete_MCRegisterSet *pData, uint32_t numEntries, uint32_t validflag) @@ -2831,7 +2836,7 @@ void iceland_convert_mc_registers( } /* find the entry in the memory range table, then populate the value to SMC's iceland_mc_reg_table */ -int iceland_convert_mc_reg_table_entry_to_smc( +static int iceland_convert_mc_reg_table_entry_to_smc( struct pp_hwmgr *hwmgr, const uint32_t memory_clock, SMU71_Discrete_MCRegisterSet *mc_reg_table_data @@ -2856,7 +2861,7 @@ int iceland_convert_mc_reg_table_entry_to_smc( return 0; } -int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, +static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, SMU71_Discrete_MCRegisters *mc_reg_table) { int result = 0; @@ -2878,7 +2883,7 @@ int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, return result; } -int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) +static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) { int result; struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); @@ -2896,21 +2901,22 @@ int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) (uint8_t *)&data->mc_reg_table, sizeof(SMU71_Discrete_MCRegisters), data->sram_end); } -int iceland_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) +static int +iceland_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) { PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; } -int iceland_enable_sclk_control(struct pp_hwmgr *hwmgr) +static int iceland_enable_sclk_control(struct pp_hwmgr *hwmgr) { PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0); return 0; } -int iceland_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) +static int iceland_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) { iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); @@ -2954,7 +2960,7 @@ int iceland_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) return 0; } -int iceland_start_dpm(struct pp_hwmgr *hwmgr) +static int iceland_start_dpm(struct pp_hwmgr *hwmgr) { iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); @@ -3905,7 +3911,7 @@ static int iceland_get_num_of_entries(struct pp_hwmgr *hwmgr) static const unsigned long PhwIceland_Magic = (unsigned long)(PHM_VIslands_Magic); -struct iceland_power_state *cast_phw_iceland_power_state( +static struct iceland_power_state *cast_phw_iceland_power_state( struct pp_hw_power_state *hw_ps) { if (hw_ps == NULL) @@ -4077,7 +4083,7 @@ static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr) * @param n : DPM level * @return The response that came from the SMC. */ -int iceland_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n) +static int iceland_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n) { iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); @@ -4100,7 +4106,7 @@ int iceland_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n) * @param n : DPM level * @return The response that came from the SMC. */ -int iceland_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n) +static int iceland_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n) { iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); @@ -4123,7 +4129,7 @@ int iceland_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n) * @param n : DPM level * @return The response that came from the SMC. */ -int iceland_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n) +static int iceland_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n) { iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); @@ -4229,7 +4235,7 @@ static int iceland_force_dpm_lowest(struct pp_hwmgr *hwmgr) return 0; } -int iceland_unforce_dpm_levels(struct pp_hwmgr *hwmgr) +static int iceland_unforce_dpm_levels(struct pp_hwmgr *hwmgr) { iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); @@ -4293,7 +4299,7 @@ static int iceland_force_dpm_level(struct pp_hwmgr *hwmgr, return ret; } -const struct iceland_power_state *cast_const_phw_iceland_power_state( +static const struct iceland_power_state *cast_const_phw_iceland_power_state( const struct pp_hw_power_state *hw_ps) { if (hw_ps == NULL) @@ -4629,7 +4635,7 @@ static int iceland_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) return 0; } -int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr) +static int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr) { iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); @@ -4769,7 +4775,7 @@ static int iceland_notify_link_speed_change_after_state_change(struct pp_hwmgr * return 0; } -int iceland_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) +static int iceland_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) { PPSMC_Result result; iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend); @@ -5142,7 +5148,8 @@ iceland_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m) seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en"); } -int iceland_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) +static int +iceland_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) { uint32_t num_active_displays = 0; struct cgs_display_info info = {0}; @@ -5166,7 +5173,7 @@ int iceland_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr * @param hwmgr the address of the powerplay hardware manager. * @return always OK */ -int iceland_program_display_gap(struct pp_hwmgr *hwmgr) +static int iceland_program_display_gap(struct pp_hwmgr *hwmgr) { uint32_t num_active_displays = 0; uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); @@ -5209,7 +5216,7 @@ int iceland_program_display_gap(struct pp_hwmgr *hwmgr) return 0; } -int iceland_display_configuration_changed_task(struct pp_hwmgr *hwmgr) +static int iceland_display_configuration_changed_task(struct pp_hwmgr *hwmgr) { iceland_program_display_gap(hwmgr); @@ -5347,7 +5354,8 @@ static inline bool iceland_are_power_levels_equal(const struct iceland_performan (pl1->pcie_lane == pl2->pcie_lane)); } -int iceland_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, +static int iceland_check_states_equal(struct pp_hwmgr *hwmgr, + const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) { const struct iceland_power_state *psa = cast_const_phw_iceland_power_state(pstate1); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_thermal.c index 527f370..a773d9a 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_thermal.c @@ -150,7 +150,7 @@ static int iceland_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) return 0; } -int iceland_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) +static int iceland_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) { return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl) == 0) ? 0 : -EINVAL; } @@ -360,7 +360,9 @@ int iceland_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) * @param Result the last failure code * @return result from set temperature range routine */ -int tf_iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) +static int +tf_iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input, + void *output, void *storage, int result) { struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend); SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; @@ -451,7 +453,8 @@ int tf_iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input, void * @param Result the last failure code * @return result from set temperature range routine */ -int tf_iceland_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) +static int tf_iceland_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) { /* If the fantable setup has failed we could have disabled PHM_PlatformCaps_MicrocodeFanControl even after this function was included in the table. * Make sure that we still think controlling the fan is OK. diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c index e58d038..c1a717c 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c @@ -34,7 +34,7 @@ int tonga_phm_powerdown_uvd(struct pp_hwmgr *hwmgr) return 0; } -int tonga_phm_powerup_uvd(struct pp_hwmgr *hwmgr) +static int tonga_phm_powerup_uvd(struct pp_hwmgr *hwmgr) { if (phm_cf_want_uvd_power_gating(hwmgr)) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, @@ -58,7 +58,7 @@ int tonga_phm_powerdown_vce(struct pp_hwmgr *hwmgr) return 0; } -int tonga_phm_powerup_vce(struct pp_hwmgr *hwmgr) +static int tonga_phm_powerup_vce(struct pp_hwmgr *hwmgr) { if (phm_cf_want_vce_power_gating(hwmgr)) return smum_send_msg_to_smc(hwmgr->smumgr, diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c index 7f9ba7f..6df929a 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c @@ -114,7 +114,7 @@ typedef enum DPM_EVENT_SRC DPM_EVENT_SRC; static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic); -struct tonga_power_state *cast_phw_tonga_power_state( +static struct tonga_power_state *cast_phw_tonga_power_state( struct pp_hw_power_state *hw_ps) { if (hw_ps == NULL) @@ -127,7 +127,7 @@ struct tonga_power_state *cast_phw_tonga_power_state( return (struct tonga_power_state *)hw_ps; } -const struct tonga_power_state *cast_const_phw_tonga_power_state( +static const struct tonga_power_state *cast_const_phw_tonga_power_state( const struct pp_hw_power_state *hw_ps) { if (hw_ps == NULL) @@ -140,7 +140,7 @@ const struct tonga_power_state *cast_const_phw_tonga_power_state( return (const struct tonga_power_state *)hw_ps; } -int tonga_add_voltage(struct pp_hwmgr *hwmgr, +static int tonga_add_voltage(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *look_up_table, phm_ppt_v1_voltage_lookup_record *record) { @@ -181,7 +181,7 @@ int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; } -uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table, +static uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table, uint32_t voltage) { uint8_t count = (uint8_t) (voltage_table->count); @@ -210,6 +210,7 @@ uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table, * @param voltage - voltage to look for * @return 0 on success */ +static uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table, uint16_t voltage) { @@ -229,7 +230,7 @@ uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table, return i-1; } -bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr) +static bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr) { /* * We return the status of Voltage Control instead of checking SCLK/MCLK DPM @@ -267,7 +268,7 @@ static uint32_t tonga_get_dpm_level_enable_mask_value( * * @param hwmgr the address of the powerplay hardware manager. */ -void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) +static void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); phw_tonga_ulv_parm *ulv = &(data->ulv); @@ -334,7 +335,7 @@ void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) } -int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr) +static int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -404,7 +405,7 @@ static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, * @param hwmgr the address of the powerplay hardware manager. * @return 2 if vddgfx returned is greater than 2V or if BIOS */ -int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr) +static int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -476,7 +477,7 @@ int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr) return 0; } -int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) +static int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -520,7 +521,7 @@ int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) return 0; } -int tonga_start_dpm(struct pp_hwmgr *hwmgr) +static int tonga_start_dpm(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -564,7 +565,7 @@ int tonga_start_dpm(struct pp_hwmgr *hwmgr) return 0; } -int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) +static int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -603,7 +604,7 @@ int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) return 0; } -int tonga_stop_dpm(struct pp_hwmgr *hwmgr) +static int tonga_stop_dpm(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -645,7 +646,7 @@ int tonga_stop_dpm(struct pp_hwmgr *hwmgr) return 0; } -int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr) +static int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr) { PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0); @@ -683,7 +684,7 @@ PPSMC_Result tonga_send_msg_to_smc_return_parameter( * @param n : DPM level * @return The response that came from the SMC. */ -int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n) +static int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); uint32_t level_mask = 1 << n; @@ -708,7 +709,7 @@ int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n) * @param n : DPM level * @return The response that came from the SMC. */ -int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n) +static int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); uint32_t level_mask = 1 << n; @@ -733,7 +734,7 @@ int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n) * @param n : DPM level * @return The response that came from the SMC. */ -int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n) +static int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -756,7 +757,7 @@ int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_set_boot_state(struct pp_hwmgr *hwmgr) +static int tonga_set_boot_state(struct pp_hwmgr *hwmgr) { /* * SMC only stores one state that SW will ask to switch too, @@ -771,7 +772,7 @@ int tonga_set_boot_state(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) +static int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend); @@ -856,7 +857,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_read_clock_registers(struct pp_hwmgr *hwmgr) +static int tonga_read_clock_registers(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -900,7 +901,7 @@ int tonga_read_clock_registers(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_get_memory_type(struct pp_hwmgr *hwmgr) +static int tonga_get_memory_type(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); uint32_t temp; @@ -920,7 +921,7 @@ int tonga_get_memory_type(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr) +static int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr) { PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1); @@ -933,7 +934,7 @@ int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr) +static int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -952,7 +953,7 @@ int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr) +static int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr) { /* * We return the status of Voltage Control instead of checking SCLK/MCLK DPM @@ -968,7 +969,7 @@ int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr) +static int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -1122,7 +1123,7 @@ static void tonga_trim_voltage_table_to_fit_state_table( * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr) +static int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -1393,7 +1394,7 @@ static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr, * @return always 0 */ -int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, +static int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table) { int result; @@ -1538,12 +1539,12 @@ static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr, * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_reset_to_default(struct pp_hwmgr *hwmgr) +static int tonga_reset_to_default(struct pp_hwmgr *hwmgr) { return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1; } -int tonga_populate_memory_timing_parameters( +static int tonga_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, @@ -1579,7 +1580,7 @@ int tonga_populate_memory_timing_parameters( * @return always 0 * This function is to be called from the SetPowerState table. */ -int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) +static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); int result = 0; @@ -2117,7 +2118,8 @@ static int tonga_populate_single_memory_level( * @param mclk the MCLK value to be used in the decision if MVDD should be high or low. * @param voltage the SMC VOLTAGE structure to be populated */ -int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern) +static int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, + SMIO_Pattern *smio_pattern) { const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -2341,7 +2343,7 @@ static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr, * @param engine_clock the engine clock to use to populate the structure * @param sclk the SMC SCLK structure to be populated */ -int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr, +static int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) { const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -2894,7 +2896,7 @@ int tonga_populate_smc_initial_state(struct pp_hwmgr *hwmgr, * @param pInput the pointer to input data (PowerState) * @return always 0 */ -int tonga_init_smc_table(struct pp_hwmgr *hwmgr) +static int tonga_init_smc_table(struct pp_hwmgr *hwmgr) { int result; tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -3131,7 +3133,7 @@ static void tonga_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr) return; } -int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) +static int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) { PPSMC_Result result; tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -3173,7 +3175,7 @@ int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) } -int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr) +static int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr) { uint32_t level, tmp; tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -3337,7 +3339,7 @@ static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr) return 0; } -int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr) +static int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); int result = 1; @@ -3598,7 +3600,7 @@ static int tonga_patch_clock_voltage_limits_with_vddgfx_leakage( return 0; } -int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr, +static int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table) { uint32_t table_size, i, j; @@ -3674,7 +3676,7 @@ static int tonga_complete_dependency_tables(struct pp_hwmgr *hwmgr) return result; } -int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr) +static int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); data->low_sclk_interrupt_threshold = 0; @@ -3682,7 +3684,7 @@ int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr) return 0; } -int tonga_setup_asic_task(struct pp_hwmgr *hwmgr) +static int tonga_setup_asic_task(struct pp_hwmgr *hwmgr) { int tmp_result, result = 0; @@ -3719,7 +3721,7 @@ int tonga_setup_asic_task(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr) +static int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr) { /* enable voltage control */ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); @@ -3732,7 +3734,7 @@ int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr) * * @param hwmgr the address of the powerplay hardware manager. */ -bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr) +static bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr) { const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); @@ -3741,12 +3743,12 @@ bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr) /*---------------------------MC----------------------------*/ -uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr) +static uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr) { return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); } -bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg) +static bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg) { bool result = true; @@ -3839,7 +3841,7 @@ bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg) return result; } -int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table) +static int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table) { uint32_t i; uint16_t address; @@ -3852,7 +3854,8 @@ int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table) return 0; } -int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_tonga_mc_reg_table *ni_table) +static int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, + phw_tonga_mc_reg_table *ni_table) { uint8_t i, j; @@ -3891,7 +3894,8 @@ int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_to * @param table the address of MCRegTable * @return always 0 */ -int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_table *table) +static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, + phw_tonga_mc_reg_table *table) { uint8_t i, j, k; uint32_t temp_reg; @@ -3973,7 +3977,7 @@ int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_tabl return 0; } -int tonga_set_valid_flag(phw_tonga_mc_reg_table *table) +static int tonga_set_valid_flag(phw_tonga_mc_reg_table *table) { uint8_t i, j; for (i = 0; i < table->last; i++) { @@ -3989,7 +3993,7 @@ int tonga_set_valid_flag(phw_tonga_mc_reg_table *table) return 0; } -int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) +static int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) { int result; tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -4047,7 +4051,7 @@ int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) * Copy one arb setting to another and then switch the active set. * arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants. */ -int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, +static int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, uint32_t arbFreqSrc, uint32_t arbFreqDest) { uint32_t mc_arb_dram_timing; @@ -4104,7 +4108,7 @@ int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, * @return always 0 * This function is to be called from the SetPowerState table. */ -int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr) +static int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr) { return tonga_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); } @@ -4115,7 +4119,7 @@ int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr) +static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr) { const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); uint32_t tmp; @@ -4140,7 +4144,8 @@ int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr) data->arb_table_start, tmp, data->sram_end); } -int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table) +static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, + SMU72_Discrete_MCRegisters *mc_reg_table) { const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); @@ -4164,7 +4169,7 @@ int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegis } /*convert register values from driver to SMC format */ -void tonga_convert_mc_registers( +static void tonga_convert_mc_registers( const phw_tonga_mc_reg_entry * pEntry, SMU72_Discrete_MCRegisterSet *pData, uint32_t numEntries, uint32_t validflag) @@ -4180,7 +4185,7 @@ void tonga_convert_mc_registers( } /* find the entry in the memory range table, then populate the value to SMC's tonga_mc_reg_table */ -int tonga_convert_mc_reg_table_entry_to_smc( +static int tonga_convert_mc_reg_table_entry_to_smc( struct pp_hwmgr *hwmgr, const uint32_t memory_clock, SMU72_Discrete_MCRegisterSet *mc_reg_table_data @@ -4205,7 +4210,7 @@ int tonga_convert_mc_reg_table_entry_to_smc( return 0; } -int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, +static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table) { int result = 0; @@ -4227,7 +4232,7 @@ int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, return result; } -int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) +static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) { int result; struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); @@ -4251,7 +4256,8 @@ int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr) +static int +tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -4273,7 +4279,7 @@ int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_enable_display_gap(struct pp_hwmgr *hwmgr) +static int tonga_enable_display_gap(struct pp_hwmgr *hwmgr) { uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); @@ -4296,7 +4302,7 @@ int tonga_enable_display_gap(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int tonga_program_voting_clients(struct pp_hwmgr *hwmgr) +static int tonga_program_voting_clients(struct pp_hwmgr *hwmgr) { tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); @@ -4327,7 +4333,7 @@ int tonga_program_voting_clients(struct pp_hwmgr *hwmgr) } -int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr) +static int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr) { int tmp_result, result = 0; @@ -4412,7 +4418,7 @@ int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr) return result; } -int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr) +static int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr) { int tmp_result, result = 0; @@ -4442,7 +4448,7 @@ int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr) return result; } -int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) +static int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) { return phm_hwmgr_backend_fini(hwmgr); } @@ -4453,7 +4459,7 @@ int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return 1 if success; otherwise appropriate error code. */ -int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr) +static int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr) { int result = 0; SMU72_Discrete_DpmTable *table = NULL; @@ -4857,7 +4863,7 @@ static int tonga_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, return 0; } -int tonga_get_power_state_size(struct pp_hwmgr *hwmgr) +static int tonga_get_power_state_size(struct pp_hwmgr *hwmgr) { return sizeof(struct tonga_power_state); } @@ -5796,7 +5802,7 @@ int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always OK */ -int tonga_program_display_gap(struct pp_hwmgr *hwmgr) +static int tonga_program_display_gap(struct pp_hwmgr *hwmgr) { struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); uint32_t num_active_displays = 0; @@ -5840,7 +5846,7 @@ int tonga_program_display_gap(struct pp_hwmgr *hwmgr) return 0; } -int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr) +static int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr) { tonga_program_display_gap(hwmgr); @@ -5898,7 +5904,7 @@ uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr) return reference_clock; } -int tonga_dpm_set_interrupt_state(void *private_data, +static int tonga_dpm_set_interrupt_state(void *private_data, unsigned src_id, unsigned type, int enabled) { @@ -5938,7 +5944,7 @@ int tonga_dpm_set_interrupt_state(void *private_data, return 0; } -int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, +static int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *thermal_interrupt_info) { int result; @@ -5965,7 +5971,8 @@ int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, return 0; } -bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) +static bool +tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) { struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); bool is_update_required = false; @@ -5993,7 +6000,10 @@ static inline bool tonga_are_power_levels_equal(const struct tonga_performance_l (pl1->pcie_lane == pl2->pcie_lane)); } -int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) +static int tonga_check_states_equal(struct pp_hwmgr *hwmgr, + const struct pp_hw_power_state *pstate1, + const struct pp_hw_power_state *pstate2, + bool *equal) { const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1); const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c index a0ffd4a..1acf321 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c @@ -131,7 +131,7 @@ static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) /** * Private Function to get the PowerPlay Table Address. */ -const void *get_powerplay_table(struct pp_hwmgr *hwmgr) +static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) { int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c index 47ef1ca..35f4574 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c @@ -138,7 +138,7 @@ int tonga_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) return 0; } -int tonga_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) +static int tonga_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) { int result; @@ -360,7 +360,8 @@ int tonga_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) * @param Result the last failure code * @return result from set temperature range routine */ -int tf_tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) +static int tf_tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input, + void *output, void *storage, int result) { struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); SMU72_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; @@ -451,7 +452,8 @@ int tf_tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input, void * * @param Result the last failure code * @return result from set temperature range routine */ -int tf_tonga_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) +static int tf_tonga_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, + void *input, void *output, void *storage, int result) { /* If the fantable setup has failed we could have disabled PHM_PlatformCaps_MicrocodeFanControl even after this function was included in the table. * Make sure that we still think controlling the fan is OK.