From patchwork Mon Nov 7 16:44:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 81123 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp1094608qge; Mon, 7 Nov 2016 08:20:53 -0800 (PST) X-Received: by 10.98.153.20 with SMTP id d20mr15201313pfe.44.1478535653228; Mon, 07 Nov 2016 08:20:53 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q86si7798323pfk.100.2016.11.07.08.20.52; Mon, 07 Nov 2016 08:20:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932717AbcKGQUj (ORCPT + 27 others); Mon, 7 Nov 2016 11:20:39 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:13786 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932658AbcKGQUM (ORCPT ); Mon, 7 Nov 2016 11:20:12 -0500 Received: from 172.24.1.36 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.36]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DUQ90171; Tue, 08 Nov 2016 00:19:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Tue, 8 Nov 2016 00:19:46 +0800 From: John Garry To: CC: , , , , , , , , John Garry Subject: [PATCH 3/3] arm64: dts: hisi: add refclk node to hip06 dts files for SAS Date: Tue, 8 Nov 2016 00:44:25 +0800 Message-ID: <1478537065-169286-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1478537065-169286-1-git-send-email-john.garry@huawei.com> References: <1478537065-169286-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We will only maintain 1 dts for D03 and there are 50MHz and 66MHz versions of D03: so we expect UEFI to update refclk rate in the fdt at boot time. Signed-off-by: John Garry Reviewed-by: Xiang Chen --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 5330abb..7b40dce 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -318,6 +318,12 @@ #size-cells = <2>; ranges; + refclk: refclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + usb_ohci: ohci@a7030000 { compatible = "generic-ohci"; reg = <0x0 0xa7030000 0x0 0x10000>; @@ -552,6 +558,7 @@ ctrl-reset-reg = <0xa60>; ctrl-reset-sts-reg = <0x5a30>; ctrl-clock-ena-reg = <0x338>; + clocks = <&refclk 0>; queue-count = <16>; phy-count = <8>; dma-coherent; @@ -594,6 +601,7 @@ ctrl-reset-reg = <0xa18>; ctrl-reset-sts-reg = <0x5a0c>; ctrl-clock-ena-reg = <0x318>; + clocks = <&refclk 0>; queue-count = <16>; phy-count = <8>; dma-coherent; @@ -635,6 +643,7 @@ ctrl-reset-reg = <0xae0>; ctrl-reset-sts-reg = <0x5a70>; ctrl-clock-ena-reg = <0x3a8>; + clocks = <&refclk 0>; queue-count = <16>; phy-count = <9>; dma-coherent;