From patchwork Fri Dec 2 05:52:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baoyou Xie X-Patchwork-Id: 86239 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp110902qgi; Thu, 1 Dec 2016 21:53:08 -0800 (PST) X-Received: by 10.84.136.135 with SMTP id 7mr93000052pll.40.1480657988001; Thu, 01 Dec 2016 21:53:08 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1si3689337plk.74.2016.12.01.21.53.07; Thu, 01 Dec 2016 21:53:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752798AbcLBFw7 (ORCPT + 25 others); Fri, 2 Dec 2016 00:52:59 -0500 Received: from mail-pf0-f175.google.com ([209.85.192.175]:34835 "EHLO mail-pf0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750888AbcLBFw6 (ORCPT ); Fri, 2 Dec 2016 00:52:58 -0500 Received: by mail-pf0-f175.google.com with SMTP id i88so50576738pfk.2 for ; Thu, 01 Dec 2016 21:52:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=2kPQErCXdT05ttBmT3hEyiQfqEjK6645X/h/+fsOeUU=; b=jaYyq42+YnOSWiqrEScxgrMT9El20ohjSmLexPV8axoZoMXcWVHPr/O/0MjqpmP/R6 mecMlp9p7uNCcdNRZ27buSk/fYut8idwEEBMCVVF6d6k4VcmUdWebDV5ctFJCb1MJ1RJ hRK9RkYZov3yvbYPWr6fgZTwWanZ1MPAaZsNs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=2kPQErCXdT05ttBmT3hEyiQfqEjK6645X/h/+fsOeUU=; b=l47EmaKTcrGYKM3d7Z2oOdGdjxOV1k7e4c2kNvX/PwY00/ahKrWbiJ4+wVCUS6vjjK xxZXT4aRKZFj6fzpSM3nrHk17D0xooz6H/glNqlgJLXY7QBxZctil/+atpnMSO+Hdk4y J/hGyx1NgQZ79o2fuYduVu356+mCcIM2Q5droOFjO2gIJzAKQqDmUCJtZLOYqtQ6jgKv wPJURGPTYs3ceSA1gTy9BJ7ir6NJe5+eGqSnlaEMbk1epr0JZnWaFMPOJrpNw1VdXQVH Shn+zJ6IwZgKvDdW4M77tk5wjUs8X2YibchdrnF15QAc8h8XA3v7Kj5BCDGwGPwkVIKz klwQ== X-Gm-Message-State: AKaTC00L3R9T2F5Dq3BSIma1TuDoxpztqmcd10W0f1SViMeDdfxOS+olbWMDvkh/hsTXE/K+ X-Received: by 10.98.70.74 with SMTP id t71mr43467598pfa.47.1480657977522; Thu, 01 Dec 2016 21:52:57 -0800 (PST) Received: from localhost.localdomain ([104.237.91.245]) by smtp.gmail.com with ESMTPSA id w17sm4181428pgm.18.2016.12.01.21.52.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 01 Dec 2016 21:52:56 -0800 (PST) From: Baoyou Xie To: robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, shawnguo@kernel.org, jun.nie@linaro.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, baoyou.xie@linaro.org, xie.baoyou@zte.com.cn, chen.chaokai@zte.com.cn, wang.qiang01@zte.com.cn Subject: [PATCH v2] arm64: dts: zx: support cpu-freq for zx296718 Date: Fri, 2 Dec 2016 13:52:36 +0800 Message-Id: <1480657956-8140-1-git-send-email-baoyou.xie@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the CPU clock phandle in CPU's node and uses operating-points-v2 to register operating points. So it can be used by cpufreq-dt driver. Signed-off-by: Baoyou Xie --- arch/arm64/boot/dts/zte/zx296718.dtsi | 39 +++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi index 7a1aed7..b44d1d1 100644 --- a/arch/arm64/boot/dts/zte/zx296718.dtsi +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi @@ -44,6 +44,7 @@ #include #include #include +#include / { compatible = "zte,zx296718"; @@ -81,6 +82,8 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + clocks = <&topcrm A53_GATE>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { @@ -88,6 +91,8 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + clocks = <&topcrm A53_GATE>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@2 { @@ -95,6 +100,8 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + clocks = <&topcrm A53_GATE>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@3 { @@ -102,6 +109,38 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + clocks = <&topcrm A53_GATE>; + operating-points-v2 = <&cluster0_opp>; + }; + }; + + cluster0_opp: opp-table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <500000>; + }; + + opp@648000000 { + opp-hz = /bits/ 64 <648000000>; + clock-latency-ns = <500000>; + }; + + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <500000>; + }; + + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <500000>; + }; + + opp@1188000000 { + opp-hz = /bits/ 64 <1188000000>; + clock-latency-ns = <500000>; }; };