From patchwork Sat Jan 21 02:26:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 92118 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp298732qgi; Fri, 20 Jan 2017 18:26:50 -0800 (PST) X-Received: by 10.98.51.70 with SMTP id z67mr12729067pfz.68.1484965610754; Fri, 20 Jan 2017 18:26:50 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m129si8493808pgm.165.2017.01.20.18.26.50; Fri, 20 Jan 2017 18:26:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752680AbdAUC0m (ORCPT + 25 others); Fri, 20 Jan 2017 21:26:42 -0500 Received: from mail-pg0-f41.google.com ([74.125.83.41]:34430 "EHLO mail-pg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752392AbdAUC0k (ORCPT ); Fri, 20 Jan 2017 21:26:40 -0500 Received: by mail-pg0-f41.google.com with SMTP id 14so28058182pgg.1 for ; Fri, 20 Jan 2017 18:26:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id; bh=XDMdugko7pCQEb7c+LquoopDAMOElQ+sWK77oKPClGc=; b=QNkkprVZfatLwCe9cF4bgldmiaVgY8aZCRnnePX0zgc+o7M50fdLMGp0QObN/obmCM cQzGy2DY7Zt602UUjzIKtunYYMN3KGW8MlGGCfJdnaJ/lV5H/mnw4lnj4fVWPzhnwHyM Z7ExQI9wzzM2k0+z8HV28rdmXGDIxg7Eo/yiw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=XDMdugko7pCQEb7c+LquoopDAMOElQ+sWK77oKPClGc=; b=sttL7tzAmdu5mfkMyksrWr3VAg228+DJH2DD616dxNuPx/DSRilgWT4bcMKovwpqtA yV3pCo6yzWZ+oHpAhdia+PQEauPbgZ81Xq2JOd5HG8SyjNitG6c+B9N63SGektHzbNff 3JMvfE+8eMBa5UKH6skHBlpu6vGIuYm9K6W9nsg4U8SvheQZOhaHlVXO5Jl6IBPLMRn4 hMfRGWQeumdhIyxSx4yZm1UwLl3GwlJ03RPVu25T4kPMkC4bjw2SwMt9a7AcSU/WjYUY Gr8ym8ZsrJLXrAbdcsBI+tzilVYn2YI5FhZm7+8OJQjbdALIxQ2ckhjQnsYZhmi+XHrA 7emA== X-Gm-Message-State: AIkVDXLTFN7L96EJmlG1I3Mqvs1zNmtA4tjd41Kso8v5kx2N7wC7QRr7doBKg1zITOiZFLn1 X-Received: by 10.99.3.5 with SMTP id 5mr20591176pgd.150.1484965600230; Fri, 20 Jan 2017 18:26:40 -0800 (PST) Received: from localhost.localdomain (61-216-91-114.HINET-IP.hinet.net. [61.216.91.114]) by smtp.gmail.com with ESMTPSA id w125sm19854006pgb.11.2017.01.20.18.26.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Jan 2017 18:26:39 -0800 (PST) From: Leo Yan To: Michael Turquette , Stephen Boyd , Leo Yan , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Guodong Xu , Haojian Zhuang , John Stultz Subject: [PATCH v2] clk: hisilicon: fix lock assignment Date: Sat, 21 Jan 2017 10:26:31 +0800 Message-Id: <1484965591-743-1-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In clock driver initialize phase the spinlock is missed to assignment to struct clkgate_separated, finally there have no locking to protect exclusive accessing for clock registers. This bug introduces the console has no output after enable coresight driver on 96boards Hikey; this is because console using UART3, which has shared the same register with coresight clock enabling bit. After applied this patch it can assign lock properly to protect exclusive accessing, and console can work well after enabled coresight modules. Fixes: 0aa0c95f743a ("clk: hisilicon: add common clock support") Signed-off-by: Leo Yan --- drivers/clk/hisilicon/clkgate-separated.c | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c index a47812f..7908bc3 100644 --- a/drivers/clk/hisilicon/clkgate-separated.c +++ b/drivers/clk/hisilicon/clkgate-separated.c @@ -120,6 +120,7 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, sclk->bit_idx = bit_idx; sclk->flags = clk_gate_flags; sclk->hw.init = &init; + sclk->lock = lock; clk = clk_register(dev, &sclk->hw); if (IS_ERR(clk))