From patchwork Wed Feb 8 23:14:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 93648 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp2926330qgi; Wed, 8 Feb 2017 15:17:27 -0800 (PST) X-Received: by 10.84.194.37 with SMTP id g34mr46333pld.105.1486595847804; Wed, 08 Feb 2017 15:17:27 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g33si8343324plb.206.2017.02.08.15.17.27; Wed, 08 Feb 2017 15:17:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751776AbdBHXRZ (ORCPT + 25 others); Wed, 8 Feb 2017 18:17:25 -0500 Received: from mail-wr0-f172.google.com ([209.85.128.172]:35261 "EHLO mail-wr0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750946AbdBHXRX (ORCPT ); Wed, 8 Feb 2017 18:17:23 -0500 Received: by mail-wr0-f172.google.com with SMTP id 89so70680051wrr.2 for ; Wed, 08 Feb 2017 15:15:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/pVK3WleTRXQIKdGHqODeuwB6fNXRwIGe4OLb8VfJ2g=; b=YbhV15oG6c1QcXvKDwyupH/d/UulnUErxCPcZH5SC+yZLTRFoQlSjyEdi6I/7EecPo psKvgHQ9xBiKD03FHDUz06NTYD6JVCWf+nh5I4hofWQUvB31sewB8dNtSr5IKw6B1ZK8 yCI1kAaCEz5GZwrwMyJjTrSN6BScRwSpiFBG8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/pVK3WleTRXQIKdGHqODeuwB6fNXRwIGe4OLb8VfJ2g=; b=SMYWNkJfjB0y0Zttrt4wJCmFmTyMW5r6ExNCuS5Q0e0i1xLiq6KidlLJ2Uavix0z17 5AuWZc/lOhrCRdSSatpx028qRCso84QdXyZB9PSLsRhnnYBQS9PODZoVNonRNHE0fKjU 73IO8AblS7DoMXtHhwvEGvNgYFZp80jUBlGqslDDKPIxOBU2vI0d4LKq7Jzc9ccRdail ynpPn7pdpJ111tR4JeJUJphhZtV+bVAvmHxRmyscYhu+H4PmVvWdswuvGPfkyECv7Quu XE5oHXZScAdGJqq9UJ9GDjNsxsWyN7u/ol3fqhxYACQjLBfDwMzkAsBZfH+pFPwEPnud achg== X-Gm-Message-State: AMke39kHmOOcxr431zzbdhn04WJ1FqHb7qwh4b/HivRvSzBFojztIboZH/2y41dQmVfIbNJY X-Received: by 10.223.141.229 with SMTP id o92mr56509wrb.22.1486595752998; Wed, 08 Feb 2017 15:15:52 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:3f16:bcf7:601c:a13b]) by smtp.gmail.com with ESMTPSA id u42sm15422821wrc.1.2017.02.08.15.15.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Feb 2017 15:15:52 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: David Engraf , Nicolas Ferre , linux-arm-kernel@lists.infradead.org (moderated list:ATMEL Timer Counter (TC) AND CLOCKSOURCE DRIVERS), linux-kernel@vger.kernel.org (open list:CLOCKSOURCE, CLOCKEVENT DRIVERS) Subject: [PATCH 04/10] clocksource/drivers/tcb_clksrc: Use 32 bit tcb as sched_clock Date: Thu, 9 Feb 2017 00:14:38 +0100 Message-Id: <1486595685-10232-4-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486595685-10232-1-git-send-email-daniel.lezcano@linaro.org> References: <20170208231208.GB12695@mai> <1486595685-10232-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: David Engraf On newer boards the TC can be read as single 32 bit value without locking. Thus the clock can be used as reference for sched_clock which is much more accurate than the jiffies implementation. Tested on a Atmel SAMA5D2 board. Signed-off-by: David Engraf Acked-by: Nicolas Ferre Signed-off-by: Daniel Lezcano --- drivers/clocksource/tcb_clksrc.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c index d4ca996..745844e 100644 --- a/drivers/clocksource/tcb_clksrc.c +++ b/drivers/clocksource/tcb_clksrc.c @@ -10,6 +10,7 @@ #include #include #include +#include /* @@ -56,11 +57,16 @@ static u64 tc_get_cycles(struct clocksource *cs) return (upper << 16) | lower; } -static u64 tc_get_cycles32(struct clocksource *cs) +static u32 tc_get_cv32(void) { return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV)); } +static u64 tc_get_cycles32(struct clocksource *cs) +{ + return tc_get_cv32(); +} + static struct clocksource clksrc = { .name = "tcb_clksrc", .rating = 200, @@ -69,6 +75,11 @@ static struct clocksource clksrc = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +static u64 notrace tc_read_sched_clock(void) +{ + return tc_get_cv32(); +} + #ifdef CONFIG_GENERIC_CLOCKEVENTS struct tc_clkevt_device { @@ -339,6 +350,9 @@ static int __init tcb_clksrc_init(void) clksrc.read = tc_get_cycles32; /* setup ony channel 0 */ tcb_setup_single_chan(tc, best_divisor_idx); + + /* register sched_clock on chips with single 32 bit counter */ + sched_clock_register(tc_read_sched_clock, 32, divided_rate); } else { /* tclib will give us three clocks no matter what the * underlying platform supports.