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[209.132.180.67]) by mx.google.com with ESMTP id s24si8331915pfj.271.2017.02.08.15.17.29; Wed, 08 Feb 2017 15:17:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752109AbdBHXR1 (ORCPT + 25 others); Wed, 8 Feb 2017 18:17:27 -0500 Received: from mail-wm0-f45.google.com ([74.125.82.45]:38067 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751052AbdBHXRX (ORCPT ); Wed, 8 Feb 2017 18:17:23 -0500 Received: by mail-wm0-f45.google.com with SMTP id r141so3286120wmg.1 for ; Wed, 08 Feb 2017 15:15:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Css91AUnQ8uM9yGeGH5kJ4rM9rCK/s2Eiz9Em7aMVIM=; b=k4DoEcTq/BppP0PttCEVbq3rSki8Vt133f7qIKf5uTzRHYPKV5FTHwFAcU4oipmytG d8U51Ev/l6u7jEgtze9bnnaZOJVZRwAk3uPFhrELe3wxXvSVmxQBCU5haHOKxOnIHRqA 8+c8CCmN75X3jOMg6bp/qAfxYMelZqv9De1nc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Css91AUnQ8uM9yGeGH5kJ4rM9rCK/s2Eiz9Em7aMVIM=; b=lfGtbEtHzQzvvf8EAJ73jqG22gUG8hEi8A8NEsQ6U362TVDCN4FpsbCTpCrf+3MYSK 14PPG/fzmcP/b8vupbN21e/8TLUb+WicTPbkA5UZVFxFrCc42TmJ9DrpCxQknfVjAi0K A7H8NvfiliBwA5PfiG9S8XHYssxOMsowm0MN5JkVQcyXQUQOAEfZw+2rcwNsvH71gCfV obtG1I3PVp7bWwQHcUYfN9xdVyrQd9+5DZ00T9cn5uJQIW25Ubc4I3YVx3ZUAZNujMCY W4R8JotV05uoYiF/v9Q4y/OehFdvPd1ckYsdwXFsrMzjC8zhTDYRfHMl/sU35MXDg8lp zlZw== X-Gm-Message-State: AMke39kPlwTRi7fkT32tGwrToFC3WMQviGDQ8/mXtQcmtJ712W4xCRy6qhzqMkJEen0FI2Rc X-Received: by 10.28.14.65 with SMTP id 62mr20217538wmo.46.1486595757749; Wed, 08 Feb 2017 15:15:57 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:3f16:bcf7:601c:a13b]) by smtp.gmail.com with ESMTPSA id u42sm15422821wrc.1.2017.02.08.15.15.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Feb 2017 15:15:57 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: Chris Brandt , Rob Herring , Rob Herring , Mark Rutland , Geert Uytterhoeven , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 05/10] clocksource/drivers/ostm: Document renesas-ostm timer DT bindings Date: Thu, 9 Feb 2017 00:14:39 +0100 Message-Id: <1486595685-10232-5-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486595685-10232-1-git-send-email-daniel.lezcano@linaro.org> References: <20170208231208.GB12695@mai> <1486595685-10232-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chris Brandt Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/renesas,ostm.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/renesas,ostm.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/timer/renesas,ostm.txt b/Documentation/devicetree/bindings/timer/renesas,ostm.txt new file mode 100644 index 0000000..be3ae0f --- /dev/null +++ b/Documentation/devicetree/bindings/timer/renesas,ostm.txt @@ -0,0 +1,30 @@ +* Renesas OS Timer (OSTM) + +The OSTM is a multi-channel 32-bit timer/counter with fixed clock +source that can operate in either interval count down timer or free-running +compare match mode. + +Channels are independent from each other. + +Required Properties: + + - compatible: must be one or more of the following: + - "renesas,r7s72100-ostm" for the r7s72100 OSTM + - "renesas,ostm" for any OSTM + This is a fallback for the above renesas,*-ostm entries + + - reg: base address and length of the register block for a timer channel. + + - interrupts: interrupt specifier for the timer channel. + + - clocks: clock specifier for the timer channel. + +Example: R7S72100 (RZ/A1H) OSTM node + + ostm0: timer@fcfec000 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec000 0x30>; + interrupts = ; + clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; + power-domains = <&cpg_clocks>; + };