From patchwork Wed Feb 8 23:14:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 93660 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp18721qgi; Wed, 8 Feb 2017 16:58:07 -0800 (PST) X-Received: by 10.98.100.69 with SMTP id y66mr498551pfb.174.1486601887508; Wed, 08 Feb 2017 16:58:07 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r7si8532991ple.302.2017.02.08.16.58.07; Wed, 08 Feb 2017 16:58:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752404AbdBIA6F (ORCPT + 25 others); Wed, 8 Feb 2017 19:58:05 -0500 Received: from mail-wm0-f46.google.com ([74.125.82.46]:36256 "EHLO mail-wm0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752096AbdBIA6E (ORCPT ); Wed, 8 Feb 2017 19:58:04 -0500 Received: by mail-wm0-f46.google.com with SMTP id c85so216397948wmi.1 for ; Wed, 08 Feb 2017 16:58:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bixArb8OCaKEYhyQWNsmRF7IUeqN0MPGnTHb7FqLwes=; b=WPS1uVjvmXzGNSd3H4U4YLL9UhWtvHGc7yJWpveVp2s0Y7eJFuAig+ijQKb81+MILO gzPH9EFrWLR0tcpjEgo2I6MIWwQsKgIy/r1FSZ+SXECArzHx433k3O7Y60OWIeRALXAw qKqwd8jyP9ApgrRwJEKIPzs9t3AQL56M3VJIw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bixArb8OCaKEYhyQWNsmRF7IUeqN0MPGnTHb7FqLwes=; b=ORK4udebOQeJTXjYrH2N8g3qPSdM5vNuqMoGnQMdXax1KilITe99RpgIcg/E59J3oo /S3FGWKE2jwqT9myFQBbsshW3UaUCm+LS1E3K+l3bdxYcit4A0NsTR+GDqH595JeBaLj X+k/VzFphCqzMQiOAFflpyVRNT11IbXGLL+PNOIMwKvjG8y4hT1Nch3rs646IiKdU0vk wVoC6tef88kC5EbZzaLB9QbfF3clxLNFiP7Yk93mVcy7iSqS7ErHwQKu8u+DNss/S2Ax l4RT0fjOqJMtDbUVjIsHNa5BVTklW707iDMxERla8enAq9vI5R6dNC+Tq73JGCXK4dBg D7XA== X-Gm-Message-State: AMke39mS0xoVkf8HjGEQj42bbj0zmzKiGmCaS5AeVpmjQvRNaT49ZEarqJyicpC7BM1y4KyF X-Received: by 10.28.127.73 with SMTP id a70mr20427983wmd.76.1486595764880; Wed, 08 Feb 2017 15:16:04 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:3f16:bcf7:601c:a13b]) by smtp.gmail.com with ESMTPSA id u42sm15422821wrc.1.2017.02.08.15.16.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Feb 2017 15:16:04 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: Ding Tianhong , Mark Rutland , Rob Herring , Rob Herring , Will Deacon , Douglas Anderson , Brian Norris , Scott Wood , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 07/10] clocksource/drivers/arm_arch_timer: Add dt binding for hisilicon-161010101 erratum Date: Thu, 9 Feb 2017 00:14:41 +0100 Message-Id: <1486595685-10232-7-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486595685-10232-1-git-send-email-daniel.lezcano@linaro.org> References: <20170208231208.GB12695@mai> <1486595685-10232-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ding Tianhong This erratum describes a bug in logic outside the core, so MIDR can't be used to identify its presence, and reading an SoC-specific revision register from common arch timer code would be awkward. So, describe it in the device tree. Signed-off-by: Ding Tianhong Acked-by: Rob Herring Signed-off-by: Mark Rutland Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index ad440a2..e926aea 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs. This also affects writes to the tval register, due to the implicit counter read. +- hisilicon,erratum-161010101 : A boolean property. Indicates the + presence of Hisilicon erratum 161010101, which says that reading the + counters is unreliable in some cases, and reads may return a value 32 + beyond the correct value. This also affects writes to the tval + registers, due to the implicit counter read. + ** Optional properties: - arm,cpu-registers-not-fw-configured : Firmware does not initialize