From patchwork Wed Mar 8 10:47:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95029 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp2292791qgd; Wed, 8 Mar 2017 02:55:41 -0800 (PST) X-Received: by 10.99.157.2 with SMTP id i2mr6072934pgd.139.1488970540967; Wed, 08 Mar 2017 02:55:40 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x188si2942986pgb.6.2017.03.08.02.55.40; Wed, 08 Mar 2017 02:55:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752619AbdCHKzk (ORCPT + 25 others); Wed, 8 Mar 2017 05:55:40 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:56921 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751465AbdCHKzf (ORCPT ); Wed, 8 Mar 2017 05:55:35 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v28AlfXM021960; Wed, 8 Mar 2017 04:47:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1488970061; bh=MIvJxFveBjyM1P4EpIB5B3299rQ/2NwNwUWVvMp9RAc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OMcJp2ZednhhAGCcTJwNWW8hX3NdbJ0E5Pf71+TJGGJNXDwT/OdfncerEF6Dxecm2 pTpnmyjNe8232eBsUUhH/3G5oZWaQV4M1zR0XS7MSqBWFGN7962BHbCFw3T6/LJfjZ InUYqRZQCKlrgaL/Ixm4i3s89J5NVIVukbk0+Nfo= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28AlfxY032318; Wed, 8 Mar 2017 04:47:41 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Wed, 8 Mar 2017 04:47:40 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v28AlJ29000570; Wed, 8 Mar 2017 04:47:34 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , Kishon Vijay Abraham I Subject: [PATCH v3 2/7] PCI: dwc: dra7xx: Populate cpu_addr_fixup ops Date: Wed, 8 Mar 2017 16:17:12 +0530 Message-ID: <1488970037-17740-3-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1488970037-17740-1-git-send-email-kishon@ti.com> References: <1488970037-17740-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Populate cpu_addr_fixup ops to extract the least 28 bits of the corresponding cpu address. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pci-dra7xx.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) -- 1.7.9.5 diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 0984baf..07c45ec 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -88,6 +88,11 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, writel(value, pcie->base + offset); } +static u64 dra7xx_pcie_cpu_addr_fixup(u64 pci_addr) +{ + return pci_addr & DRA7XX_CPU_TO_BUS_ADDR; +} + static int dra7xx_pcie_link_up(struct dw_pcie *pci) { struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); @@ -152,11 +157,6 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); - pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR; - pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR; - pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR; - pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR; - dw_pcie_setup_rc(pp); dra7xx_pcie_establish_link(dra7xx); @@ -329,6 +329,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, } static const struct dw_pcie_ops dw_pcie_ops = { + .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup, .link_up = dra7xx_pcie_link_up, };