From patchwork Wed Apr 19 16:44:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 97662 Delivered-To: patch@linaro.org Received: by 10.140.109.52 with SMTP id k49csp418415qgf; Wed, 19 Apr 2017 10:10:55 -0700 (PDT) X-Received: by 10.84.225.145 with SMTP id u17mr4482072plj.91.1492621855664; Wed, 19 Apr 2017 10:10:55 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x84si2167795pfi.125.2017.04.19.10.10.55; Wed, 19 Apr 2017 10:10:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966654AbdDSQp2 (ORCPT + 16 others); Wed, 19 Apr 2017 12:45:28 -0400 Received: from foss.arm.com ([217.140.101.70]:43630 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966629AbdDSQpY (ORCPT ); Wed, 19 Apr 2017 12:45:24 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9F75E16BA; Wed, 19 Apr 2017 09:45:13 -0700 (PDT) Received: from leverpostej.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3301D3F4FF; Wed, 19 Apr 2017 09:45:12 -0700 (PDT) From: Mark Rutland To: daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, fu.wei@linaro.org, lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org, marc.zyngier@arm.com Subject: [PATCH 04/16] clocksource: arm_arch_timer: move enums and defines to header file Date: Wed, 19 Apr 2017 17:44:21 +0100 Message-Id: <1492620273-30037-5-git-send-email-mark.rutland@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492620273-30037-1-git-send-email-mark.rutland@arm.com> References: <1492620273-30037-1-git-send-email-mark.rutland@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fu Wei To support the arm_arch_timer via ACPI we need to share defines and enums between the driver and the ACPI parser code. So we split out the relevant defines and enums into arm_arch_timer.h. No functional change. Signed-off-by: Fu Wei Acked-by: Mark Rutland Tested-by: Xiongfeng Wang Signed-off-by: Mark Rutland --- drivers/clocksource/arm_arch_timer.c | 11 ----------- include/clocksource/arm_arch_timer.h | 12 ++++++++++++ 2 files changed, 12 insertions(+), 11 deletions(-) -- 1.9.1 diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 94e355b..04218c1 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -55,8 +55,6 @@ #define CNTV_TVAL 0x38 #define CNTV_CTL 0x3c -#define ARCH_TIMER_TYPE_CP15 BIT(0) -#define ARCH_TIMER_TYPE_MEM BIT(1) static unsigned arch_timers_present __initdata; static void __iomem *arch_counter_base; @@ -69,15 +67,6 @@ struct arch_timer { #define to_arch_timer(e) container_of(e, struct arch_timer, evt) static u32 arch_timer_rate; - -enum arch_timer_ppi_nr { - ARCH_TIMER_PHYS_SECURE_PPI, - ARCH_TIMER_PHYS_NONSECURE_PPI, - ARCH_TIMER_VIRT_PPI, - ARCH_TIMER_HYP_PPI, - ARCH_TIMER_MAX_TIMER_PPI -}; - static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI]; static struct clock_event_device __percpu *arch_timer_evt; diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h index caedb74..b898637 100644 --- a/include/clocksource/arm_arch_timer.h +++ b/include/clocksource/arm_arch_timer.h @@ -16,9 +16,13 @@ #ifndef __CLKSOURCE_ARM_ARCH_TIMER_H #define __CLKSOURCE_ARM_ARCH_TIMER_H +#include #include #include +#define ARCH_TIMER_TYPE_CP15 BIT(0) +#define ARCH_TIMER_TYPE_MEM BIT(1) + #define ARCH_TIMER_CTRL_ENABLE (1 << 0) #define ARCH_TIMER_CTRL_IT_MASK (1 << 1) #define ARCH_TIMER_CTRL_IT_STAT (1 << 2) @@ -34,6 +38,14 @@ enum arch_timer_reg { ARCH_TIMER_REG_TVAL, }; +enum arch_timer_ppi_nr { + ARCH_TIMER_PHYS_SECURE_PPI, + ARCH_TIMER_PHYS_NONSECURE_PPI, + ARCH_TIMER_VIRT_PPI, + ARCH_TIMER_HYP_PPI, + ARCH_TIMER_MAX_TIMER_PPI +}; + #define ARCH_TIMER_PHYS_ACCESS 0 #define ARCH_TIMER_VIRT_ACCESS 1 #define ARCH_TIMER_MEM_PHYS_ACCESS 2