From patchwork Mon Jun 5 23:21:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 103101 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp1008517obh; Mon, 5 Jun 2017 16:25:45 -0700 (PDT) X-Received: by 10.84.218.8 with SMTP id q8mr17832179pli.135.1496705145154; Mon, 05 Jun 2017 16:25:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496705145; cv=none; d=google.com; s=arc-20160816; b=CGRFLQCUUB31TUMPl/lQ7y70SHYWLOup7jpNUAwK9wvbqNwDbjdAbNpia5FttZekCq 7AI+JNhnTR2LTm3KJKjk+NM4Jn9UNrrbVoHz/GYG3m9AelGucowTTf0mx5Togf2/rq/v qzpxpey+lia8AEjTpns4zM/oaAlkjWLIZoH9O3htkNMkhqnrrL5rhoFoi+r8OsckXo3c yIU7R5I22vRI5sfEiWcOTrkGAWGUTC0AqNmjXdLAqTZyx84fDq3HEvWw7NTc2FshWaDK p350cYKtbw3XteoErSuFnwvhExlL5dz0IQhwmmQoU5o6xCK1Opm5Cn2CO7iuoVlDrJyJ QQKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=/fsVBEcNz1BAkf+t3CMO31hBKIYSvE9lyaCGs7G3+WY=; b=nO640yl5fW/+fmh+CurcN80axk1zrvhpYy5nC5oi9CteseyZNv8QRMy6o94a2U72zj qt2pLqWUXIFGGz7tkrYJ94L0VZvBSohJJmm07n1nHpTyBszmmLlTEiQZZzPELhYzEvI3 O74O1JgamGFva3WEZWvXovXwTRJcxaqdrFd1Y1BgXYj5Y7g5Ug3quUaE9IYJWvzlpvvd ixJE/lsjvZH2DjwXGb0Imh8DZ2CctB2CDCxowGWEx2ONgjFMlayiGYpWt9K7J9dpriO3 EsjmFYLW/5oxt89DVjCPxZRkbSlX8+mpgMYZJ7MCPY8gbfCJv8DdSWomxYsVa2oU+MDx 3T1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q20si10759518pfl.414.2017.06.05.16.25.44; Mon, 05 Jun 2017 16:25:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751380AbdFEXZZ (ORCPT + 25 others); Mon, 5 Jun 2017 19:25:25 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:32337 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751350AbdFEXZX (ORCPT ); Mon, 5 Jun 2017 19:25:23 -0400 Received: from grover.sesame (FL1-118-110-19-204.osk.mesh.ad.jp [118.110.19.204]) (authenticated) by conuserg-10.nifty.com with ESMTP id v55NMD5o004412; Tue, 6 Jun 2017 08:22:44 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v55NMD5o004412 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1496704964; bh=/fsVBEcNz1BAkf+t3CMO31hBKIYSvE9lyaCGs7G3+WY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=x56mIGQ1B4VCpsacELNKvuxlaPr9m6qYUNZyIC9XwbF3zA+EgKqURRL2yuBjSC81q fFxveju7SrbttCScUyOnT5eGpybtJu7iFmFJ4SCuViLg0ZBESkPVJbs9LQcZvl+s6e 7tUK9Yzgl/W0a5uPAozGuIe8c6FjXa21NzRou38I+YOingpmRdvJ97pkFmt+5yw1Pt DOa93D3l7rkWZv6T6zOMiJSNvew7+XozGYLOxSK0lccRXfv20XAuOuoeldUHlIyvew fEwaF+h1YqWWVPtQ+4U1tMkMV9YznJ7yk+MVHcgioOzZr49PgQLCgulFJOgkBBEt6h z+G7gW01i3s0A== X-Nifty-SrcIP: [118.110.19.204] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger Subject: [PATCH v4 14/23] mtd: nand: denali: switch over to cmd_ctrl instead of cmdfunc Date: Tue, 6 Jun 2017 08:21:53 +0900 Message-Id: <1496704922-12261-15-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496704922-12261-1-git-send-email-yamada.masahiro@socionext.com> References: <1496704922-12261-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The NAND_CMD_SET_FEATURES support is missing from denali_cmdfunc(). This is needed for nand_onfi_set_features(). Besides, we see /* TODO: Read OOB data */ comment line. It would be possible to add more commands along with the current implementation, but having ->cmd_ctrl() seems a better approach from the discussion with Boris [1]. Rely on the default ->cmdfunc() from the framework and implement the driver's own ->cmd_ctrl(). Also add ->write_byte(), which is needed for write direction commands. [1] https://lkml.org/lkml/2017/3/15/97 Signed-off-by: Masahiro Yamada --- Changes in v4: None Changes in v3: None Changes in v2: - Newly added drivers/mtd/nand/denali.c | 104 +++++++++++++++++++++++----------------------- 1 file changed, 52 insertions(+), 52 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 4d46202..083dfc7 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -230,20 +230,16 @@ static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, return denali->irq_status; } -/* resets a specific device connected to the core */ -static void reset_bank(struct denali_nand_info *denali) +static uint32_t denali_check_irq(struct denali_nand_info *denali) { + unsigned long flags; uint32_t irq_status; - denali_reset_irq(denali); - - iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); - - irq_status = denali_wait_for_irq(denali, - INTR__RST_COMP | INTR__TIME_OUT); + spin_lock_irqsave(&denali->irq_lock, flags); + irq_status = denali->irq_status; + spin_unlock_irqrestore(&denali->irq_lock, flags); - if (!(irq_status & INTR__RST_COMP)) - dev_err(denali->dev, "reset bank failed.\n"); + return irq_status; } /* @@ -273,6 +269,42 @@ static uint8_t denali_read_byte(struct mtd_info *mtd) return ioread32(denali->flash_mem + 0x10); } +static void denali_write_byte(struct mtd_info *mtd, uint8_t byte) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + + index_addr(denali, MODE_11 | BANK(denali->flash_bank) | 2, byte); +} + +static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + uint32_t type; + + if (ctrl & NAND_CLE) + type = 0; + else if (ctrl & NAND_ALE) + type = 1; + else + return; + + /* + * Some commands are followed by chip->dev_ready or chip->waitfunc. + * irq_status must be cleared here to catch the R/B# interrupt later. + */ + if (ctrl & NAND_CTRL_CHANGE) + denali_reset_irq(denali); + + index_addr(denali, MODE_11 | BANK(denali->flash_bank) | type, dat); +} + +static int denali_dev_ready(struct mtd_info *mtd) +{ + struct denali_nand_info *denali = mtd_to_denali(mtd); + + return !!(denali_check_irq(denali) & INTR__INT_ACT); +} + /* * sends a pipeline command operation to the controller. See the Denali NAND * controller's user guide for more information (section 4.2.3.6). @@ -824,7 +856,13 @@ static void denali_select_chip(struct mtd_info *mtd, int chip) static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) { - return 0; + struct denali_nand_info *denali = mtd_to_denali(mtd); + uint32_t irq_status; + + /* R/B# pin transitioned from low to high? */ + irq_status = denali_wait_for_irq(denali, INTR__INT_ACT); + + return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL; } static int denali_erase(struct mtd_info *mtd, int page) @@ -845,46 +883,6 @@ static int denali_erase(struct mtd_info *mtd, int page) return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL; } -static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, - int page) -{ - struct denali_nand_info *denali = mtd_to_denali(mtd); - uint32_t addr, irq_status; - int wait_ready = 0; - - switch (cmd) { - case NAND_CMD_PARAM: - wait_ready = 1; - break; - case NAND_CMD_STATUS: - case NAND_CMD_READID: - break; - case NAND_CMD_RESET: - reset_bank(denali); - break; - case NAND_CMD_READOOB: - /* TODO: Read OOB data */ - return; - default: - pr_err(": unsupported command received 0x%x\n", cmd); - return; - } - - denali_reset_irq(denali); - - addr = MODE_11 | BANK(denali->flash_bank); - index_addr(denali, addr | 0, cmd); - if (col != -1) - index_addr(denali, addr | 1, col); - - if (!wait_ready) - return; - - irq_status = denali_wait_for_irq(denali, INTR__INT_ACT); - if (!(irq_status & INTR__INT_ACT)) - dev_err(denali->dev, "failed to issue command 0x%x\n", cmd); -} - #define DIV_ROUND_DOWN_ULL(ll, d) \ ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; }) @@ -1240,8 +1238,10 @@ int denali_init(struct denali_nand_info *denali) /* register the driver with the NAND core subsystem */ chip->select_chip = denali_select_chip; - chip->cmdfunc = denali_cmdfunc; chip->read_byte = denali_read_byte; + chip->write_byte = denali_write_byte; + chip->cmd_ctrl = denali_cmd_ctrl; + chip->dev_ready = denali_dev_ready; chip->waitfunc = denali_waitfunc; /* clk rate info is needed for setup_data_interface */ if (denali->clk_x_rate)