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[209.132.180.67]) by mx.google.com with ESMTP id a7si651899plt.37.2017.06.14.05.44.56; Wed, 14 Jun 2017 05:44:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=I9yuzBmA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752753AbdFNMoy (ORCPT + 25 others); Wed, 14 Jun 2017 08:44:54 -0400 Received: from mail-wr0-f180.google.com ([209.85.128.180]:35753 "EHLO mail-wr0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752530AbdFNMlL (ORCPT ); Wed, 14 Jun 2017 08:41:11 -0400 Received: by mail-wr0-f180.google.com with SMTP id q97so188225316wrb.2 for ; Wed, 14 Jun 2017 05:41:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=96rWRNhAOakG06Tcjr9z/8cHNjzfaP5jpoVml7JywlQ=; b=I9yuzBmAhGp3dmQ+VxnWpuLNUA8OrJk6M/ufYo1Y1ctjDjsdqmMkKAvMQQf9g0PNRC D3DeYBkBDSM2B9kD2JRNZm/nMHpJSkQKJhwO5XMiHSiwI8FaBoscIJ2HS4BTQ80KtYEL rPFsEqrfG8U0tIOXvCJu7CcyJNhHJdSgo09BY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=96rWRNhAOakG06Tcjr9z/8cHNjzfaP5jpoVml7JywlQ=; b=XQAzT6ERWl5qZ54Qn4Z0GMmQI8goZ7MwFLtiNuS4aBqCJcLDjqnOK1OzzGL3G+Y10D nWyLOZLtBYysfpKoPkvcXIkFqNnctWLOy4iPFAhO9kUgkyBcwbEENo576p6TMJSDE9sB 7UlInd8Kqv5kpo3Atw/HVQlRbDqQk3LvR0kWyhJEYQWJtPcHblxbur9BbTgtVJo5Lp11 PgSIcGTZdHJvlSJpnZfKl/xBGQq/mD3Du++YjbtvwEQfQUjDsv7c6hK2iI2MqHLCkhf2 0zk8Pt+QXRzdcyX/Vwe0k/zlw4QfvTC3t9U2szkHRQkqY4ysgPgvzP8nWxKq0hjJ61pJ h6fg== X-Gm-Message-State: AKS2vOxaNx5FUOxv6+nOxCAMFZ/GkUw3cuUxzQ2amIIftoLJltgHHWeg suZ7yHwSQwKjPjlg X-Received: by 10.223.129.183 with SMTP id 52mr355508wra.71.1497444064492; Wed, 14 Jun 2017 05:41:04 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:19a:b336:54d7:46e9]) by smtp.gmail.com with ESMTPSA id 80sm1457015wmg.17.2017.06.14.05.41.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 05:41:03 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Joel Stanley , Jonas Jensen Subject: [PATCH 07/23] clocksource/drivers/fttmr010: Switch to use TIMER2 src Date: Wed, 14 Jun 2017 14:39:28 +0200 Message-Id: <1497443984-12371-7-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> References: <20170614123800.GH2261@mai> <1497443984-12371-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij This switches the clocksource to TIMER2 like the Moxart driver does. Mainly to make it more similar to the Moxart/Aspeed driver but also because it seems more neat to use the timers in order: use timer 1, then timer 2. Cc: Joel Stanley Tested-by: Jonas Jensen Signed-off-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index 9df14cf..2d915d1 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -49,9 +49,6 @@ #define TIMER_1_CR_UPDOWN BIT(9) #define TIMER_2_CR_UPDOWN BIT(10) #define TIMER_3_CR_UPDOWN BIT(11) -#define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN | \ - TIMER_3_CR_ENABLE | \ - TIMER_3_CR_UPDOWN) #define TIMER_1_INT_MATCH1 BIT(0) #define TIMER_1_INT_MATCH2 BIT(1) @@ -80,7 +77,7 @@ static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt) static u64 notrace fttmr010_read_sched_clock(void) { - return readl(local_fttmr->base + TIMER3_COUNT); + return readl(local_fttmr->base + TIMER2_COUNT); } static int fttmr010_timer_set_next_event(unsigned long cycles, @@ -230,19 +227,21 @@ static int __init fttmr010_timer_init(struct device_node *np) */ writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); writel(0, fttmr010->base + TIMER_INTR_STATE); - writel(TIMER_DEFAULT_FLAGS, fttmr010->base + TIMER_CR); + /* Enable timer 1 count up, timer 2 count up */ + writel((TIMER_1_CR_UPDOWN | TIMER_2_CR_ENABLE | TIMER_2_CR_UPDOWN), + fttmr010->base + TIMER_CR); /* * Setup free-running clocksource timer (interrupts * disabled.) */ local_fttmr = fttmr010; - writel(0, fttmr010->base + TIMER3_COUNT); - writel(0, fttmr010->base + TIMER3_LOAD); - writel(0, fttmr010->base + TIMER3_MATCH1); - writel(0, fttmr010->base + TIMER3_MATCH2); - clocksource_mmio_init(fttmr010->base + TIMER3_COUNT, - "FTTMR010-TIMER3", + writel(0, fttmr010->base + TIMER2_COUNT); + writel(0, fttmr010->base + TIMER2_LOAD); + writel(0, fttmr010->base + TIMER2_MATCH1); + writel(0, fttmr010->base + TIMER2_MATCH2); + clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, + "FTTMR010-TIMER2", fttmr010->tick_rate, 300, 32, clocksource_mmio_readl_up); sched_clock_register(fttmr010_read_sched_clock, 32,