From patchwork Mon Jun 26 13:38:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 106329 Delivered-To: patch@linaro.org Received: by 10.140.101.48 with SMTP id t45csp86315qge; Mon, 26 Jun 2017 06:40:34 -0700 (PDT) X-Received: by 10.84.128.107 with SMTP id 98mr255488pla.285.1498484434432; Mon, 26 Jun 2017 06:40:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498484434; cv=none; d=google.com; s=arc-20160816; b=f/yeSnazB0sDpKSr+L00SGX1dcnvNkS4DAmsiuZKF4HGXwYG8xpfqWURpNDh5aHIka 1KUiaejTDdKKRfSdg9HHSDlN4LaxdqdYK5X+tY/PW5clNOIqZlIJwsif0n2vDQ2eFrpw RuN8m9YQ9knyMmDh6OoBqMFvdddNdFa9hpglGeAodXkXpkpQcMHWvL8dyZGyOUqrjDXa njETh2stBcs+3uX8ztM5CnL9/fP5klf6/dNU+dx2BClkCEAiWoHlaSVHXY3yOvjnekNg HOmleeJF/CG33JRT81Ujm+zzQFM4WE38PX7OheUcgh2y1f7JSnfkBG4/Y+4vZ4QUnPtd aX+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=xdRy7Gm07VdVX4GzVcSEqnYgNHpGIsyOKo2nEdr01O0=; b=Ec9ha97hykDvw5LM/3a0S551F84RYH2YNOxMPvi6r1aOrdodMqAkbUfvOJ+TFDlJVe t07G+C2QQTm7d1SyIQV8Cq/2AqmFE1DQlTozNh6kyO0RnH0b8CJX3QAbLozgSI0LbF7W bduhXmRKErXilWNHUlcv2qpczC18pxssbDvkre66kF6+52TL2GhKtsWyR9FQHnL4YzK9 SoMbOx3sI9FJO0UBnOb9fPAOELpAHcAE/hXAKaRVgfO92TGAF0RAbO+Q9bYBNBmQJCoK aVyCz7N7WdUtfyXtwvWMgxPSE6owOhonQs6Mc29J1345hd6kXb4lvrkqsROlqjl1Fsim P9aw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v18si66190pgo.569.2017.06.26.06.40.34; Mon, 26 Jun 2017 06:40:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752579AbdFZNkV (ORCPT + 25 others); Mon, 26 Jun 2017 09:40:21 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:8799 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752396AbdFZNje (ORCPT ); Mon, 26 Jun 2017 09:39:34 -0400 Received: from 172.30.72.56 (EHLO DGGEML401-HUB.china.huawei.com) ([172.30.72.56]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AQZ51690; Mon, 26 Jun 2017 21:39:30 +0800 (CST) Received: from localhost (10.177.23.164) by DGGEML401-HUB.china.huawei.com (10.3.17.32) with Microsoft SMTP Server id 14.3.301.0; Mon, 26 Jun 2017 21:39:20 +0800 From: Zhen Lei To: Will Deacon , Joerg Roedel , linux-arm-kernel , iommu , Robin Murphy , linux-kernel CC: Zefan Li , Xinwei Hu , "Tianhong Ding" , Hanjun Guo , Zhen Lei , John Garry Subject: [PATCH 4/5] iommu/arm-smmu: add support for unmap a memory range with only one tlb sync Date: Mon, 26 Jun 2017 21:38:49 +0800 Message-ID: <1498484330-10840-5-git-send-email-thunder.leizhen@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1498484330-10840-1-git-send-email-thunder.leizhen@huawei.com> References: <1498484330-10840-1-git-send-email-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.164] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.59510E92.0192, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 3781b651141444572d08b21ae36ce573 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 1. remove tlb_sync operation in "unmap" 2. make sure each "unmap" will always be followed by tlb sync operation The resultant effect is as below: unmap memory page-1 tlb invalidate page-1 ... unmap memory page-n tlb invalidate page-n tlb sync Signed-off-by: Zhen Lei --- drivers/iommu/arm-smmu.c | 10 ++++++++++ drivers/iommu/io-pgtable-arm-v7s.c | 32 +++++++++++++++++++++----------- 2 files changed, 31 insertions(+), 11 deletions(-) -- 2.5.0 diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index b8d069a..74ca6eb 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1402,6 +1402,15 @@ static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, return ops->unmap(ops, iova, size); } +static void arm_smmu_unmap_tlb_sync(struct iommu_domain *domain) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; + + if (ops && ops->unmap_tlb_sync) + ops->unmap_tlb_sync(ops); +} + static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, dma_addr_t iova) { @@ -1698,6 +1707,7 @@ static struct iommu_ops arm_smmu_ops = { .attach_dev = arm_smmu_attach_dev, .map = arm_smmu_map, .unmap = arm_smmu_unmap, + .unmap_tlb_sync = arm_smmu_unmap_tlb_sync, .map_sg = default_iommu_map_sg, .iova_to_phys = arm_smmu_iova_to_phys, .add_device = arm_smmu_add_device, diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c index a55fd38..325c1c6 100644 --- a/drivers/iommu/io-pgtable-arm-v7s.c +++ b/drivers/iommu/io-pgtable-arm-v7s.c @@ -370,6 +370,8 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data, for (i = 0; i < num_entries; i++) if (ARM_V7S_PTE_IS_TABLE(ptep[i], lvl)) { + size_t unmapped; + /* * We need to unmap and free the old table before * overwriting it with a block entry. @@ -378,8 +380,10 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data, size_t sz = ARM_V7S_BLOCK_SIZE(lvl); tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl); - if (WARN_ON(__arm_v7s_unmap(data, iova + i * sz, - sz, lvl, tblp) != sz)) + unmapped = __arm_v7s_unmap(data, iova + i * sz, + sz, lvl, tblp); + io_pgtable_tlb_sync(&data->iop); + if (WARN_ON(unmapped != sz)) return -EINVAL; } else if (ptep[i]) { /* We require an unmap first */ @@ -626,7 +630,6 @@ static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *data, /* Also flush any partial walks */ io_pgtable_tlb_add_flush(iop, iova, blk_size, ARM_V7S_BLOCK_SIZE(lvl + 1), false); - io_pgtable_tlb_sync(iop); ptep = iopte_deref(pte[i], lvl); __arm_v7s_free_table(ptep, lvl + 1, data); } else { @@ -653,13 +656,15 @@ static int arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova, size_t size) { struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); - size_t unmapped; - unmapped = __arm_v7s_unmap(data, iova, size, 1, data->pgd); - if (unmapped) - io_pgtable_tlb_sync(&data->iop); + return __arm_v7s_unmap(data, iova, size, 1, data->pgd); +} + +static void arm_v7s_unmap_tlb_sync(struct io_pgtable_ops *ops) +{ + struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); - return unmapped; + io_pgtable_tlb_sync(&data->iop); } static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops, @@ -724,6 +729,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, data->iop.ops = (struct io_pgtable_ops) { .map = arm_v7s_map, .unmap = arm_v7s_unmap, + .unmap_tlb_sync = arm_v7s_unmap_tlb_sync, .iova_to_phys = arm_v7s_iova_to_phys, }; @@ -822,7 +828,7 @@ static int __init arm_v7s_do_selftests(void) .quirks = IO_PGTABLE_QUIRK_ARM_NS | IO_PGTABLE_QUIRK_NO_DMA, .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, }; - unsigned int iova, size, iova_start; + unsigned int iova, size, unmapped, iova_start; unsigned int i, loopnr = 0; selftest_running = true; @@ -877,7 +883,9 @@ static int __init arm_v7s_do_selftests(void) size = 1UL << __ffs(cfg.pgsize_bitmap); while (i < loopnr) { iova_start = i * SZ_16M; - if (ops->unmap(ops, iova_start + size, size) != size) + unmapped = ops->unmap(ops, iova_start + size, size); + ops->unmap_tlb_sync(ops); + if (unmapped != size) return __FAIL(ops); /* Remap of partial unmap */ @@ -896,7 +904,9 @@ static int __init arm_v7s_do_selftests(void) while (i != BITS_PER_LONG) { size = 1UL << i; - if (ops->unmap(ops, iova, size) != size) + unmapped = ops->unmap(ops, iova, size); + ops->unmap_tlb_sync(ops); + if (unmapped != size) return __FAIL(ops); if (ops->iova_to_phys(ops, iova + 42))