From patchwork Tue Jun 27 09:26:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 106408 Delivered-To: patch@linaro.org Received: by 10.140.101.48 with SMTP id t45csp996421qge; Tue, 27 Jun 2017 02:29:10 -0700 (PDT) X-Received: by 10.84.141.3 with SMTP id 3mr2121656plu.227.1498555750790; Tue, 27 Jun 2017 02:29:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498555750; cv=none; d=google.com; s=arc-20160816; b=l8w58xu5kMFKPnV5nJxahOdbjCdc3KnGTfPrT5V/2aJV0c1VymgwILnkRKUgcHVQF4 ntU6PUg06VfFf0hiD6Jwr0giB/sfjTFgXDrVot1zUgowojXE+tuZ/fkl3gV1Y6tORFAU 2APBxZDgS09E7W9Z7CySmiOwQ0mPZ4N5zHRN/MPT7xI0jAfiQWykwbqLFh7LafJKlXW7 dlfPnRrlzYzp8xb8mCu5p7Za1KgYxP3qKUeaJQOpGHHhyTOoq6IhGPFfFzGf7RhhhXdg ZDBdBiXe0U7Am4c6bLqLuy+e1cfbG12Idyjxxk0kZ/Bi5h2UPEck8xcPdoaLyuIP2UfO USRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=jdNJWMDZf1Dv0K90xhnKgz0LnXdjEGF6e/vqTY2riWU=; b=GjkbijgegdmmfyznkSn/s9zgdHAex35Uqf1QHnwhfj3+dkEAX+fobr2UZs0dbZBd6z fwK3QLoUscFS/yAm1NWp02EPXSy7wQ7EgQOtr/rhrbgouEu5RCPlZOPs2kIl56izc0iQ coI7OmQ4BF/a7fi/R4+TFaQVb4co4+gpIM4Jdm0DtPXnZx6vNHMUETwt9l+svV5ckqVL C31GBz1CElSKfzs/UNMDwnSDXF4JPmoLepFQCT7CJ670tFIVV3zM5jJIwfp1xtKxrT/R hVZtxW7j4HAE3Fy7IW6cYghHKvnUhHSf3a+6i6cyhPc3Hb8jHpNFRdrFb6Q9v0m1Q4c2 nRLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=eJGoHzsx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s80si1603828pfs.171.2017.06.27.02.29.10; Tue, 27 Jun 2017 02:29:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=eJGoHzsx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752530AbdF0J2r (ORCPT + 25 others); Tue, 27 Jun 2017 05:28:47 -0400 Received: from mail-wm0-f53.google.com ([74.125.82.53]:37914 "EHLO mail-wm0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752271AbdF0J2a (ORCPT ); Tue, 27 Jun 2017 05:28:30 -0400 Received: by mail-wm0-f53.google.com with SMTP id b184so20403146wme.1 for ; Tue, 27 Jun 2017 02:28:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jdNJWMDZf1Dv0K90xhnKgz0LnXdjEGF6e/vqTY2riWU=; b=eJGoHzsxd1a/GFL+/8jaju5urEP5nUdHaSHX76TMKYkV/H+TXtm6tmLjzQF3WQlHTa YjVYPg/6e1PyT+VjzZz1eUpZyoAGkNJJlfgkt+AYejEYVlYzjPj2QPfs1WUqXhnfFQaw a1zczB40UoxGcMxUPvJSBugdkN8467OckAA8I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jdNJWMDZf1Dv0K90xhnKgz0LnXdjEGF6e/vqTY2riWU=; b=DocbW/UMZ8lXwruRNs8hFgrbyuGi01axbQFm9Eu7c8MxBMerlIAXixfC7FlmnknsXC ufd39qaranu5RltNNGEYEhDPQv8g8W2Ak1Bh1f1q1Aa6qIr2w2eOAqtmT06HJC/SfMKB 5spAzVFIzJJwZIw+gQLwvREq/+cbqEmKtRSM9c3M623tJXG2zcbkmPZaoBgyXZBWMCjb L48DTS28QUmbwRVfL0hFUoC2L2rywvKak/q3IH20PtBJwybTzhrn2FcDRkgftv6UdKQN GXJ/PX8fFaZdcPv79/lCoAUd729QpCctzGtrrQdE/4R0KHc3SAXISVNW+g8cNjHg/ywN S77Q== X-Gm-Message-State: AKS2vOzxZnBchKHQ6n9tzp6bvwSH7JVc/t2pwHlvYd6FauiJRmc65zW8 8DBw4ZHFtfhvAk5k X-Received: by 10.28.105.85 with SMTP id e82mr2638731wmc.122.1498555708986; Tue, 27 Jun 2017 02:28:28 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:110f:661:6b72:192e]) by smtp.gmail.com with ESMTPSA id g2sm16159798wrg.69.2017.06.27.02.28.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Jun 2017 02:28:28 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Alexandre Belloni , Nicolas Ferre , linux-arm-kernel@lists.infradead.org (moderated list:ATMEL Timer Counter (TC) AND CLOCKSOURCE DRIVERS) Subject: [PATCH 3/5] clocksource/drivers/tcb_clksrc: Make IO endian agnostic Date: Tue, 27 Jun 2017 11:26:58 +0200 Message-Id: <1498555620-25094-3-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498555620-25094-1-git-send-email-daniel.lezcano@linaro.org> References: <20170627092239.GE2479@mai> <1498555620-25094-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexandre Belloni Now that AVR32 is gone, we can use the proper IO accessors that are correctly handling endianness. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre Signed-off-by: Daniel Lezcano --- drivers/clocksource/tcb_clksrc.c | 58 ++++++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 29 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c index 828729c..59e8aee 100644 --- a/drivers/clocksource/tcb_clksrc.c +++ b/drivers/clocksource/tcb_clksrc.c @@ -57,9 +57,9 @@ static u64 tc_get_cycles(struct clocksource *cs) raw_local_irq_save(flags); do { - upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)); - lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV)); - } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV))); + upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)); + lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV)); + } while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV))); raw_local_irq_restore(flags); return (upper << 16) | lower; @@ -67,7 +67,7 @@ static u64 tc_get_cycles(struct clocksource *cs) static u64 tc_get_cycles32(struct clocksource *cs) { - return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV)); + return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV)); } void tc_clksrc_suspend(struct clocksource *cs) @@ -147,8 +147,8 @@ static int tc_shutdown(struct clock_event_device *d) struct tc_clkevt_device *tcd = to_tc_clkevt(d); void __iomem *regs = tcd->regs; - __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR)); - __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); + writel(0xff, regs + ATMEL_TC_REG(2, IDR)); + writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); if (!clockevent_state_detached(d)) clk_disable(tcd->clk); @@ -166,9 +166,9 @@ static int tc_set_oneshot(struct clock_event_device *d) clk_enable(tcd->clk); /* slow clock, count up to RC, then irq and stop */ - __raw_writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE | + writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR)); - __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); + writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); /* set_next_event() configures and starts the timer */ return 0; @@ -188,25 +188,25 @@ static int tc_set_periodic(struct clock_event_device *d) clk_enable(tcd->clk); /* slow clock, count up to RC, then irq and restart */ - __raw_writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO, + writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR)); - __raw_writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC)); + writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC)); /* Enable clock and interrupts on RC compare */ - __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); + writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); /* go go gadget! */ - __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs + + writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs + ATMEL_TC_REG(2, CCR)); return 0; } static int tc_next_event(unsigned long delta, struct clock_event_device *d) { - __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC)); + writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC)); /* go go gadget! */ - __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, + writel_relaxed(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, tcaddr + ATMEL_TC_REG(2, CCR)); return 0; } @@ -230,7 +230,7 @@ static irqreturn_t ch2_irq(int irq, void *handle) struct tc_clkevt_device *dev = handle; unsigned int sr; - sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR)); + sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR)); if (sr & ATMEL_TC_CPCS) { dev->clkevt.event_handler(&dev->clkevt); return IRQ_HANDLED; @@ -290,43 +290,43 @@ static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx) static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx) { /* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */ - __raw_writel(mck_divisor_idx /* likely divide-by-8 */ + writel(mck_divisor_idx /* likely divide-by-8 */ | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP /* free-run */ | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */ | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */ tcaddr + ATMEL_TC_REG(0, CMR)); - __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA)); - __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC)); - __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ - __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); + writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA)); + writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC)); + writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ + writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); /* channel 1: waveform mode, input TIOA0 */ - __raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */ + writel(ATMEL_TC_XC1 /* input: TIOA0 */ | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP, /* free-run */ tcaddr + ATMEL_TC_REG(1, CMR)); - __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */ - __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); + writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */ + writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); /* chain channel 0 to channel 1*/ - __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR); + writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR); /* then reset all the timers */ - __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); + writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); } static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx) { /* channel 0: waveform mode, input mclk/8 */ - __raw_writel(mck_divisor_idx /* likely divide-by-8 */ + writel(mck_divisor_idx /* likely divide-by-8 */ | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP, /* free-run */ tcaddr + ATMEL_TC_REG(0, CMR)); - __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ - __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); + writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ + writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); /* then reset all the timers */ - __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); + writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); } static int __init tcb_clksrc_init(void)