From patchwork Thu Jan 4 12:50:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123413 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11389761qgn; Thu, 4 Jan 2018 04:51:36 -0800 (PST) X-Google-Smtp-Source: ACJfBovNFlJmixHxt6O06vEPlCD0/TLu/y29psHaJOHt8TgBG7gek/LveuAWotjqLxUQutiF1mRi X-Received: by 10.98.156.204 with SMTP id u73mr4662960pfk.8.1515070296536; Thu, 04 Jan 2018 04:51:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070296; cv=none; d=google.com; s=arc-20160816; b=dA1++4fUXDCrDUNHLO88Dcyc4I2hggVpK7aQ/C2iMQj3cJYkctHk8UDDa/Rfpwp88w j7AP9i8r8Ol2KS8Ckhdn0D2vXaoHH0AESWWFUNju4U0wMcY9ZFAjPmwsvkmH/IAh/LgB BOOWCgjDXJyIcy28fCZUqsMKAVIIBJWPWvdTgRyUZLUliESIEUp7w/qdVAYBiqqPNfw9 /BAE7HNCITwn9BQaRK4asq9yNZpAkLKvky5j+vuKFaGj9qOPBVK6mrW0iL9HJWTrkL71 EbOfoFZh76pm8knyrSwcx0c4eef1p8NHYxkqHg42/fVGcb5+b/Ve5a3AtoDNu1UqFUyH yCpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=ISYh0PkE1j9BwfAi+cGjUoGaBFRtbCXSQ5n7YU7T+jA=; b=PLG8kARqZXa4MD2U7sA+bP9p4ZfenOQtJbQ2PkO9Zys75z/ZoW9dddqYlXukT3Udfw 6LcvOgeWFVBeB2Tu/UfROtKtpO1hteIrvyr7/wz1jOup/dDR4JaHV/A7Ddi89E2hz7Ci 0YrOOtyy3FFhHjY2IAZYBF29TeFQMrUOpX0k5ob6kqXTNZCQjxgoh9gFZZqAb4RaTuQa g/h+naKJrots3LzW/HuWM8HIOxrhUZtN0DsiCfvu9V93yCjdJRZhUvJCsfDM9FuROzZF CDn6Y4p4GX6bj7siCAIz6/LNIZZOUAfzEEJpBA41gH9uU1GLbhDBOvbDDna6OaagpT0O Q1sQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j88nY+oI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i186si2288929pfg.286.2018.01.04.04.51.36; Thu, 04 Jan 2018 04:51:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j88nY+oI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752931AbeADMvc (ORCPT + 27 others); Thu, 4 Jan 2018 07:51:32 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:46444 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752713AbeADMvZ (ORCPT ); Thu, 4 Jan 2018 07:51:25 -0500 Received: by mail-wm0-f68.google.com with SMTP id r78so3295801wme.5 for ; Thu, 04 Jan 2018 04:51:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ISYh0PkE1j9BwfAi+cGjUoGaBFRtbCXSQ5n7YU7T+jA=; b=j88nY+oITtOCKiIUsG1wfaWuvTjJaHbNZG9QDMI2AcXZ1MP/UBH8PHC9x6FQa1gSSq 0U5aSXXWV3e+JU7LMKdTKqfEiDASCxwFy4UDlLfnhn9qxcKP4GMBrUeWsOT/+9bF20/B MzF2t0+8F2IWwjNSlXdu+qOWegJh9I/k26+As= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ISYh0PkE1j9BwfAi+cGjUoGaBFRtbCXSQ5n7YU7T+jA=; b=Bo0WmpV3foSl34v4UWPMsqmrQt5J+3re2P5l4xwdPKS+qPNDUQPrctwwXmp4CXPL95 6uG0+bqRIauqat23Dd7xm8+R3asD7mZjR2eRlXN7xtuYNEOkCo3qhEW+Twjdiqmsa3bi AfDpUZ7eiL616CWmDGhf7NTA11KHGRm/qFUUUlcwyXsm7Jr2wSu0+6NQeaqVJcJgB+BT 524K6GsspetEjBjdvXdA2llecVaC+4uJUkHsQMe3XZZa3nA0BTmY5TKeo1AWYMNoIl0/ foOADKPe9+TBd5GngHJsCDiHAKtApwgXn4FJCvsSzKvps4JvVFRiD6685Sn3HUhxa3jK 1tMg== X-Gm-Message-State: AKGB3mI5+PCzxByS9smlis9eQ1C/oQ1hJHVQZLFjClP+QBWQTBBI9pEh I0p4k8qYFYLLCBK2g8h7oT7R7A== X-Received: by 10.28.140.206 with SMTP id o197mr3623274wmd.43.1515070284183; Thu, 04 Jan 2018 04:51:24 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:23 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org, Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 06/12] clocksource/drivers/stm32: Encapsulate the timer width sorting out function Date: Thu, 4 Jan 2018 13:50:22 +0100 Message-Id: <1515070228-10481-7-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to clarify and encapsulate the code for the next changes move the timer width check into a function and add some documentation. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-stm32.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 14b7a2b..862134e 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -80,9 +80,27 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) return IRQ_HANDLED; } +/** + * stm32_timer_width - Sort out the timer width (32/16) + * @to: a pointer to a timer-of structure + * + * Write the 32bits max value and read/return the result. If the timer + * is a 32bits width, the result will be UINT_MAX, otherwise it will + * be truncated by the 16bits register to USHRT_MAX. + * + * Returns UINT_MAX if the timer is 32bits width, USHRT_MAX if it is a + * 16bits width. + */ +static u32 __init stm32_timer_width(struct timer_of *to) +{ + writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR); + + return readl_relaxed(timer_of_base(to) + TIM_ARR); +} + static void __init stm32_clockevent_init(struct timer_of *to) { - unsigned long max_delta; + u32 width = 0; int prescaler; to->clkevt.name = to->np->full_name; @@ -93,10 +111,8 @@ static void __init stm32_clockevent_init(struct timer_of *to) to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; - /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); - if (max_delta == ~0U) { + width = stm32_timer_width(to); + if (width == UINT_MAX) { prescaler = 1; to->clkevt.rating = 250; } else { @@ -115,10 +131,10 @@ static void __init stm32_clockevent_init(struct timer_of *to) to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); clockevents_config_and_register(&to->clkevt, - timer_of_rate(to), 0x1, max_delta); + timer_of_rate(to), 0x1, width); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - to->np, max_delta == UINT_MAX ? 32 : 16); + to->np, width == UINT_MAX ? 32 : 16); } static int __init stm32_timer_init(struct device_node *node)