From patchwork Thu Jan 4 15:08:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 123438 Delivered-To: patch@linaro.org Received: by 10.80.135.92 with SMTP id 28csp6822436edv; Thu, 4 Jan 2018 07:11:41 -0800 (PST) X-Google-Smtp-Source: ACJfBouiXIHgTWCIdb5nqSZjOqDBKIO6va4FbUd3iylHEMvCIILsYt2vh1lGIff5G1fMaIpbDNkO X-Received: by 10.159.207.132 with SMTP id z4mr4903647plo.440.1515078701497; Thu, 04 Jan 2018 07:11:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515078701; cv=none; d=google.com; s=arc-20160816; b=zKzx+wbSDwCWPu1clz4ZKkxpdlO6Tz4nwBW0Xa6i58iLwNvxMVn2Goi0e1xe/VfWG0 6uQ6PfdqwTYMohItMlh/lknkgRoj3LOSxiRDr9IU1DF+UxRSGFMNOwxS4tSqoBWkEcsL IWbjJRne5D14+XPVolyS4qVToj/CUCF7oVyNbztqGBPBpvBft/oVbEu3tLTeqPcNKm1o IX9MKuhp9VHoaK7EtTL0wfVQ+izWH+dsfYU4FE4TUBU5MaEgaw1EStieTLo08QjFPu+c Kz7nsh0+WHfOKsLTgpeC5pSepRy7LqhDvtq7tOqZ0m7mfkkchOYNr4BiVy/TqekaJQWu i7pQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=nttO8VxrACQgRB9QLPa8QR6+GM0DElU11YOsB77CT1w=; b=Qlzb7ayqK8qBverD9t7HMkHLdOYpWqPYKyeclyWvlbjRef1d0fdqs4+il0ijQ9E5lF qDhZ1fWDfgGB4b19hF9pj7+cBVHfsbmmMvwIaLGzcJr5Dg7jy3xW/2QWvYyZqNYfPReZ R4PWUoXE1ssGi0pMXRemJUUrFz+H2vBX9RZaeKXOfg+AFmRfUdjpVw+vn6jomhn5jAd5 LM/NQk1CZfKfJtlZCpIG3kCxBRLaPAQBI+A8/yJnt6Bs+y9fK9d/UTJZTKN7oF/krzMk /el5UUs+8hgd6qaStTxLkArrbiwXym36hGFxKQQa1vqEQR/3fnSQF7MsPvhYHEIFPoR8 XjAQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g62si2148912pgc.428.2018.01.04.07.11.41; Thu, 04 Jan 2018 07:11:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753522AbeADPKd (ORCPT + 22 others); Thu, 4 Jan 2018 10:10:33 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:33810 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753375AbeADPIl (ORCPT ); Thu, 4 Jan 2018 10:08:41 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6660F1650; Thu, 4 Jan 2018 07:08:41 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 389FC3F6CF; Thu, 4 Jan 2018 07:08:41 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id C479E1AE0F28; Thu, 4 Jan 2018 15:08:40 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org, linux-kernel@vger.kernel.org, Will Deacon Subject: [PATCH 06/11] arm64: Move post_ttbr_update_workaround to C code Date: Thu, 4 Jan 2018 15:08:30 +0000 Message-Id: <1515078515-13723-7-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515078515-13723-1-git-send-email-will.deacon@arm.com> References: <1515078515-13723-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier We will soon need to invoke a CPU-specific function pointer after changing page tables, so move post_ttbr_update_workaround out into C code to make this possible. Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon --- arch/arm64/include/asm/assembler.h | 13 ------------- arch/arm64/kernel/entry.S | 2 +- arch/arm64/mm/context.c | 9 +++++++++ arch/arm64/mm/proc.S | 3 +-- 4 files changed, 11 insertions(+), 16 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index c45bc94f15d0..cee60ce0da52 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -476,17 +476,4 @@ alternative_endif mrs \rd, sp_el0 .endm -/* - * Errata workaround post TTBRx_EL1 update. - */ - .macro post_ttbr_update_workaround -#ifdef CONFIG_CAVIUM_ERRATUM_27456 -alternative_if ARM64_WORKAROUND_CAVIUM_27456 - ic iallu - dsb nsh - isb -alternative_else_nop_endif -#endif - .endm - #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index b9feb587294d..6aa112baf601 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -277,7 +277,7 @@ alternative_else_nop_endif * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache * corruption). */ - post_ttbr_update_workaround + bl post_ttbr_update_workaround .endif 1: .if \el != 0 diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 1cb3bc92ae5c..c1e3b6479c8f 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -239,6 +239,15 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) cpu_switch_mm(mm->pgd, mm); } +/* Errata workaround post TTBRx_EL1 update. */ +asmlinkage void post_ttbr_update_workaround(void) +{ + asm volatile(ALTERNATIVE("nop; nop; nop", + "ic iallu; dsb nsh; isb", + ARM64_WORKAROUND_CAVIUM_27456, + CONFIG_CAVIUM_ERRATUM_27456)); +} + static int asids_init(void) { asid_bits = get_cpu_asid_bits(); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 3146dc96f05b..6affb68a9a14 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -145,8 +145,7 @@ ENTRY(cpu_do_switch_mm) isb msr ttbr0_el1, x0 // now update TTBR0 isb - post_ttbr_update_workaround - ret + b post_ttbr_update_workaround // Back to C code... ENDPROC(cpu_do_switch_mm) .pushsection ".idmap.text", "ax"