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[209.132.180.67]) by mx.google.com with ESMTP id h10si1147429pgs.458.2018.01.23.21.48.14; Tue, 23 Jan 2018 21:48:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I4E6uvum; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752583AbeAXFsM (ORCPT + 28 others); Wed, 24 Jan 2018 00:48:12 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:36738 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752481AbeAXFsK (ORCPT ); Wed, 24 Jan 2018 00:48:10 -0500 Received: by mail-pg0-f68.google.com with SMTP id k68so1999517pga.3 for ; Tue, 23 Jan 2018 21:48:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3rbNW3xDNb/+Hjv6vdIBgT3G0o9MU79RUdkKmHfcaVc=; b=I4E6uvumSTZYuFGorVISApEdgwRkygFDQYkqbrJKH2LieL1XZ+wFZCXHvwp3eUqQtb GvtFovyNzHLoJ2X/W9DTxhM33wYPkS5cpiv5cqAILQpTvFFqowlR6/BEaeBwrjPPi1de kzJhMydDJEm+Ti1eGqXs80/QGRvuZQHJ4CzHY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3rbNW3xDNb/+Hjv6vdIBgT3G0o9MU79RUdkKmHfcaVc=; b=TIKMN1V27eyTmZRuoRmz00cMgdAcjFGkOCiudv0Qj/RkKS9Y129HQEnWFmwGznQnhV hwpoFztG9HT8Q9Z0UnHjmoOWsQ0NyaLaYZ8vlM+4nySXUvAXS7xGKerKfDrJ6bpeq5h7 /5Leutwik3WGk//frHncGmQ9xIOTX3hxqLY4QhQfc2GY/KMgvkcyil53rPiKXI7lNnAZ Q64kIGQsbZu5QVaEscJAeO86KVGqdFev+lVNkGvgN8NsaENUbFo3VgAHMwXSVqxppCtS dEuNzCbzRMjzzc2//JgLe2uhkQ5ISAmay5gEAyI4Sz1rzuuT0LUtWG7/ajewy82g6gAv jZmQ== X-Gm-Message-State: AKwxytdF+qAq67E4YFX4IJqogzzj98V47ihHS379LMN5hmslFkeatUbk PYyZHuKrjrF2nNtgrZYGwpJrlw== X-Received: by 2002:a17:902:24a2:: with SMTP id w31-v6mr6027155pla.262.1516772889393; Tue, 23 Jan 2018 21:48:09 -0800 (PST) Received: from localhost.localdomain ([45.56.152.94]) by smtp.gmail.com with ESMTPSA id f188sm8524519pfc.22.2018.01.23.21.48.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Jan 2018 21:48:08 -0800 (PST) From: Shawn Guo To: Kishon Vijay Abraham I Cc: Rob Herring , Jianguo Sun , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, project-aspen-dev@linaro.org, Shawn Guo Subject: [PATCH v5 RESEND 2/3] dt-bindings: add bindings doc for hi3798cv200 combphy Date: Wed, 24 Jan 2018 13:47:36 +0800 Message-Id: <1516772857-3580-3-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516772857-3580-1-git-send-email-shawn.guo@linaro.org> References: <1516772857-3580-1-git-send-email-shawn.guo@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jianguo Sun It adds the device tree bindings for PCIE/SATA/USB3 combo PHY found on HiSilicon STB SoCs. Signed-off-by: Jianguo Sun Signed-off-by: Shawn Guo Acked-by: Rob Herring --- .../bindings/phy/phy-hi3798cv200-combphy.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt new file mode 100644 index 000000000000..17b0c761370a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt @@ -0,0 +1,59 @@ +HiSilicon STB PCIE/SATA/USB3 PHY + +Required properties: +- compatible: Should be "hisilicon,hi3798cv200-combphy" +- reg: Should be the address space for COMBPHY configuration and state + registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and + PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC. +- #phy-cells: Should be 1. The cell number is used to select the phy mode + as defined in . +- clocks: The phandle to clock provider and clock specifier pair. +- resets: The phandle to reset controller and reset specifier pair. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties. + +Optional properties: +- hisilicon,fixed-mode: If the phy device doesn't support mode select + but a fixed mode setting, the property should be present to specify + the particular mode. +- hisilicon,mode-select-bits: If the phy device support mode select, + this property should be present to specify the register bits in + peripheral controller, as a 3 integers tuple: + . + +Notes: +- Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only + one of them should be present. +- The device node should be a child of peripheral controller that contains + COMBPHY configuration/state and PERI_CTRL register used to select PHY mode. + Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller + bindings. + +Examples: + +perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + combphy0: phy@850 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x850 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY0_CLK>; + resets = <&crg 0x188 4>; + hisilicon,fixed-mode = ; + }; + + combphy1: phy@858 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x858 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY1_CLK>; + resets = <&crg 0x188 12>; + hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; + }; +};