From patchwork Mon Feb 26 15:04:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 129663 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp299842lja; Mon, 26 Feb 2018 07:05:26 -0800 (PST) X-Google-Smtp-Source: AH8x227e5QO5ZMigmPMAiQI0pKNRm9SxjWmbMSM6Wbalqu5k1S0gMBYAqMZerBKU9eoioE79/4uT X-Received: by 2002:a17:902:b2c6:: with SMTP id x6-v6mr10812864plw.285.1519657526175; Mon, 26 Feb 2018 07:05:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657526; cv=none; d=google.com; s=arc-20160816; b=rX7dNmUkFLXQBZT1DpKzNWFjWGGo+7M6SGSU+vbxU/ZMg/SKA6Q8SKBW1HD1C5GDRg yorKjBIoke3DEM8J1RW5T5qaeLzsZbdV4QKtJ4AZj4AdJv67QefjH6+p2KJHVA+UOpg/ td9yFbmXqcBKDOl8kglTKfPTgW7jDV4OdZ0u2ALfXrfZW7fm8981mN7mZT56a1vA6R7q +QCg+uqbpAy8jgyj77U784+ttZrnHcExq5XabDWALeG9HG0vwN9Lik6cLRQ/e3oRwpyi e4cfgui1PWrWyiYa70tYni6zA7iYEUjo7R4ItF2m1HYs9ZAsai+s+DErHDvnr3rftnHi a1EA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=0AQKq1mKVG0qdHu+zvxXwUHAuFLOceouIwgaHLTE/PU=; b=rDELrYHmvYdqj6eT9GGiot7l19UDxatpsGazBZYoaPTUX6STfOb+AnFaigREBuZmvF jphRlvDsIdY/6IC0bs8pDDOSJGAXKWzKrIifJhMIt13NEHCkhgFTOlXuDt98dLXqlIhr Qhv3hA/IlW5DzNF+bLk27nXSSHKRlO86X8k8VeVI13NE6jlsTiA1L8K9uI6bjqoCXWTe 1Hocg//BUyMDPUSiT6Z507KHa7FjUzrm1ByKbMICN6G5BclL9E6g+3TJQRCAnj8+WELV KLCbvhlxKLW0j3rjvUTJ3uR3ZSIO1TGrzu4UQgqYuKf0H8eM1OkweQdyP81jW2lqlPWR fe+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j5si1634647pgp.193.2018.02.26.07.05.25; Mon, 26 Feb 2018 07:05:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754095AbeBZPFJ (ORCPT + 28 others); Mon, 26 Feb 2018 10:05:09 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51150 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753944AbeBZPFA (ORCPT ); Mon, 26 Feb 2018 10:05:00 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2EB1E164F; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EC17B3F487; Mon, 26 Feb 2018 07:04:59 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 773381AE53AB; Mon, 26 Feb 2018 15:05:01 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RFC PATCH v2 03/12] asm-generic: Move some macros from linux/bitops.h to a new bits.h file Date: Mon, 26 Feb 2018 15:04:51 +0000 Message-Id: <1519657500-15094-4-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1519657500-15094-1-git-send-email-will.deacon@arm.com> References: <1519657500-15094-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation for implementing the asm-generic atomic bitops in terms of atomic_long_*, we need to prevent asm/atomic.h implementations from pulling in linux/bitops.h. A common reason for this include is for the BITS_PER_BYTE definition, so move this and some other BIT and masking macros into a new header file, asm-generic/bits.h Signed-off-by: Will Deacon --- include/asm-generic/bits.h | 26 ++++++++++++++++++++++++++ include/linux/bitops.h | 22 +--------------------- 2 files changed, 27 insertions(+), 21 deletions(-) create mode 100644 include/asm-generic/bits.h -- 2.1.4 diff --git a/include/asm-generic/bits.h b/include/asm-generic/bits.h new file mode 100644 index 000000000000..738f8038440b --- /dev/null +++ b/include/asm-generic/bits.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_GENERIC_BITS_H +#define __ASM_GENERIC_BITS_H +#include + +#define BIT(nr) (1UL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) +#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) +#define BITS_PER_BYTE 8 + +/* + * Create a contiguous bitmask starting at bit position @l and ending at + * position @h. For example + * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. + */ +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define GENMASK_ULL(h, l) \ + (((~0ULL) - (1ULL << (l)) + 1) & \ + (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + +#endif /* __ASM_GENERIC_BITS_H */ diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 4cac4e1a72ff..57ba7f67b360 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -2,29 +2,9 @@ #ifndef _LINUX_BITOPS_H #define _LINUX_BITOPS_H #include +#include -#ifdef __KERNEL__ -#define BIT(nr) (1UL << (nr)) -#define BIT_ULL(nr) (1ULL << (nr)) -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) -#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) -#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) -#define BITS_PER_BYTE 8 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) -#endif - -/* - * Create a contiguous bitmask starting at bit position @l and ending at - * position @h. For example - * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. - */ -#define GENMASK(h, l) \ - (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) - -#define GENMASK_ULL(h, l) \ - (((~0ULL) - (1ULL << (l)) + 1) & \ - (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) extern unsigned int __sw_hweight8(unsigned int w); extern unsigned int __sw_hweight16(unsigned int w);