From patchwork Mon Mar 5 14:48:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 130639 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2771741lja; Mon, 5 Mar 2018 06:50:11 -0800 (PST) X-Google-Smtp-Source: AG47ELsXVKPN+W5V7YVM9K8vvdXupFJhliM4f7ugl+GU7I/aniQs6oSD2manCMNueMNxJhisjvbJ X-Received: by 2002:a17:902:7142:: with SMTP id u2-v6mr13438698plm.257.1520261410955; Mon, 05 Mar 2018 06:50:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520261410; cv=none; d=google.com; s=arc-20160816; b=Tw63KvEQ0EqEcr+osoJUdgf5Rd2zX9WK5hCqva/sC0IuibnrnJMkELYbNl+kkAX8LH kpDinOsxEAxg8JZs4X+TNP2laspcDps4Z2i5HJ9dLHM2JKNU1+FvMJV77oQv77e3ndO0 X3YbgLN253cmTHdOrAfTcwH5ITzsLzBggMpodJg3dC4s73tHHNV4IXB+tIBrZtxh264T 6F7oBstyQ7iGckKLB1ESTbvkgca0cdg4o0vgBGC7WyiMGPZAl3hSsxWBHkyqH9CVs/f0 P2IGe4O9QltBtS+UmZnOGT5DTOreVMRc3G9DQKiLrEb0nnAz+KViyd8rDn/Yk7tSARsE lWVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=Gtz7KVgQJwEDSN2D+ha3eZEMI2hv9v0Pa/HFB5aivxE=; b=LFJtvp2wR3CYHd/RE+rKV4BTdcoq5qf0/KPEPovLsfn0DY80Ly2eKOGmfftJNbWpY8 kXDCBmYSEHnNXGDMVkJLX538LbRUABKPC9EA6ZIdy2DVFkeRw1SlvBlWWk+hyxFtouM8 v/ztyrt0ToMQRYYQDrEX5U9NPIISpXQ0sVr6P5MP5oC7JVaM+V/kJtE1Z1Z0PLL7DXg2 ud4a2twTof86VBaOnLvfX2Ra7TKpHYEgtpACPnegN61QcvbPFRTB7nnI6AxX/aTp4GYO agifWbRt1cArLsj9cOCYdyhrzEu+csYbXnygdOt677Wyw2Pt3zFKzmZlPhtcPz03ckvo znmQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i6si8403643pgv.519.2018.03.05.06.50.10; Mon, 05 Mar 2018 06:50:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932365AbeCEOuF (ORCPT + 28 others); Mon, 5 Mar 2018 09:50:05 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:6142 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752462AbeCEOtz (ORCPT ); Mon, 5 Mar 2018 09:49:55 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 3234CA8B0A605; Mon, 5 Mar 2018 22:49:34 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.361.1; Mon, 5 Mar 2018 22:49:26 +0800 From: John Garry To: , , , CC: , , , , Xiaofei Tan , John Garry Subject: [PATCH v3 2/8] scsi: hisi_sas: support the property of signal attenuation for v2 hw Date: Mon, 5 Mar 2018 22:48:44 +0800 Message-ID: <1520261330-204596-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1520261330-204596-1-git-send-email-john.garry@huawei.com> References: <1520261330-204596-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan The register SAS_PHY_CTRL is configured according to signal quality. The signal quality is calculated by signal attenuation of hardware physical link. It may be different for different PCB layout. So, in order to give better support to new board, this patch add support to reading the devicetree property, "hisilicon,signal-attenuation". Of course, we still keep an default value in driver to adapt old board. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 39 +++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 4ccb61e..42b3fd6 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -406,6 +406,17 @@ struct hisi_sas_err_record_v2 { __le32 dma_rx_err_type; }; +struct signal_attenuation_s { + u32 de_emphasis; + u32 preshoot; + u32 boost; +}; + +struct sig_atten_lu_s { + const struct signal_attenuation_s *att; + u32 sas_phy_ctrl; +}; + static const struct hisi_sas_hw_error one_bit_ecc_errors[] = { { .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF), @@ -1130,9 +1141,16 @@ static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba) } } +static const struct signal_attenuation_s x6000 = {9200, 0, 10476}; +static const struct sig_atten_lu_s sig_atten_lu[] = { + { &x6000, 0x3016a68 }, +}; + static void init_reg_v2_hw(struct hisi_hba *hisi_hba) { struct device *dev = hisi_hba->dev; + u32 sas_phy_ctrl = 0x30b9908; + u32 signal[3]; int i; /* Global registers init */ @@ -1176,9 +1194,28 @@ static void init_reg_v2_hw(struct hisi_hba *hisi_hba) hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1); hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); + /* Get sas_phy_ctrl value to deal with TX FFE issue. */ + if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation", + signal, ARRAY_SIZE(signal))) { + for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) { + const struct sig_atten_lu_s *lookup = &sig_atten_lu[i]; + const struct signal_attenuation_s *att = lookup->att; + + if ((signal[0] == att->de_emphasis) && + (signal[1] == att->preshoot) && + (signal[2] == att->boost)) { + sas_phy_ctrl = lookup->sas_phy_ctrl; + break; + } + } + + if (i == ARRAY_SIZE(sig_atten_lu)) + dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n"); + } + for (i = 0; i < hisi_hba->n_phy; i++) { hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855); - hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908); + hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl); hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d); hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0); hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);